Patents Represented by Attorney William L. Zitelli

Find this attorney in the Justia Lawyer Directory

  • Method of post-implementation simulation of a HDL design
    Patent number: 7086017
    Abstract: A method of post-implementation simulation of a hardware description language (HDL) net list file, that does not match a HDL design file from which it was synthesized, comprises the steps of: creating a remap file which translates ports between the HDL net list file and the HDL design file; and simulating the HDL net list file utilizing the remap file and a (HDL) test bench file created for pre-implementation simulation of the HDL design file. The method may be executed in an integrated software environment or a batch software environment.
    Type: Grant
    Filed: June 10, 2002
    Date of Patent: August 1, 2006
    Assignee: Xilinx, Inc.
    Inventor: Andrew M. Bloom