Abstract: An extraction method and an integrated cell for extracting a binary value based on a propagation of an edge of a triggering signal in two electric paths, including across two voltage supply terminals: two parallel branches each including, in series, a resistor for differentiating the electric paths; a read transistor, the junction point of the resistor and of the read transistor of each branch defining an output terminal of the cell, and the gate of the read transistor of each branch being connected to the output terminal of the other branch; and a selection transistor.

Abstract: A method for manufacturing, in a monolithic circuit including a substrate, an inductance and a through via, including the step of forming, from a first surface of the substrate, at least one trench according to the contour of the inductance to be formed; forming by laser in the substrate a through hole at the location desired for the via; simultaneously insulating the surface of the trench and of the hole; and depositing a conductive material in the trench and at least on the hole walls.

Abstract: The invention concerns a load pump for phase-locking loop comprising a first current source (14), a second current source (16), several switches (M1, M2, M3, M4) adapted to communicate the first and/or the second current source with the load pump output (OUT). The second current source is driven by control means (18) adapted to store a physical quantity corresponding to the value of the current (11) supplied by the first current source (14), so that the value of the current (12) supplied by the second current source is substantially equal to the value of current (11) supplied by the first current source.

Abstract: A monolithic bidirectional switch formed in a semiconductor substrate of type N, including a first main vertical thyristor, the rear surface layer of which is of type P, a second main vertical thyristor, the rear surface layer of which is of type N, an auxiliary vertical thyristor, the rear surface layer of which is of type P and is common with that of the first main thyristor, a peripheral region of type P especially connecting the rear surface layer of the auxiliary thyristor to the layer of this thyristor located on the other side of the substrate, a first metallization on the rear surface side, a second metallization on the front surface side connecting the front surface layers of the first and second thyristors. An additional region has a function of isolating the rear surface of the auxiliary thyristor and the first metallization.

Abstract: A device of protection of at least one circuit supplied by a voltage obtained from at least one inductive element, including a switch for short-circuiting the supply provided by the inductive element, and circuitry for turning on the switch when the supply voltage exceeds a predetermined threshold and for turning it off when it is smaller than the threshold.

Abstract: A data reception unit for receiving a plurality of data streams over a data channel, the data streams being received as amounts of data and each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream, the data reception unit comprising: a data stream memory comprising a plurality of data stream storage areas, each for storing data from a respective one of a set of the data streams, and an escape buffer; a first storage information memory for holding first storage information for facilitating storage in the respective data stream storage area of data from the set of the data streams; and a data storage controller for, for each received amount of data, receiving the identity portion of the amount of data and performing a storage operation comprising: accessing the first storage information memory; and if the first storage information memory holds first storage information for the data stream identified by the identity portion, storing the

Abstract: A method for manufacturing DRAM cells in a semiconductor wafer including MOS control transistors and capacitors, the source/drain regions and the gates of the control transistors being covered with a protection layer and with an insulating layer, in which the capacitors are formed at the level of openings formed in the insulating layer which extend to the protection layer covering the gates, and in which first capacitor electrodes are connected to source/drain regions of the control transistors by conductive vias crossing the insulating layer and the protection layer.

Abstract: A DRAM formed of an array of cells, each of which includes a capacitive memory point and a control transistor. The array is formed of the repetition of an elementary pattern extending over three rows and three columns and including six cells arranged so that each of the three rows and each of the three columns of the elementary pattern includes two cells, wherein each column of the elementary pattern includes a first and a second bit line, each first and second bit line being connected to one half of the memory cells included by the column.

Abstract: To enable a processor connected to a host computer to run programs that are dynamically loaded by the host, a stack is loaded into its memory, and the location of the stack, or information enabling that location to be found are stored in a memory location reserved as a vector. The programs are then dynamically loaded into said memory; and a set location in the stack is used to store the entry point into the dynamically loaded file.

Abstract: A filter is formed as an integrated circuit by resistive and capacitive elements and includes, for connection to ground, at least two separate pads of a chip designed to be connected individually to at least two separate terminals of a package.

Abstract: A method for differentiating integrated circuits implementing identical functions by storage of a binary code in a non-volatile storage element provided in each circuit, including providing, for each circuit of a same reticle, a selective implantation of dopants of its storage element which is different from the selective implantations of dopants of the storage elements of the other circuits.

Abstract: A method for manufacturing a contact between a semiconductor substrate and a doped polysilicon layer deposited on the substrate with an interposed insulating layer, wherein elements adapted to making the insulating layer permeable to the migration of dopants from the polysilicon layer to the substrate are implanted.

Abstract: A computer system includes instruction fetch circuitry for dispatching fetched instructions to a pipelined execution unit, data memory access circuitry and emulator circuitry for use in debug operations, said emulator circuitry including error indicating circuitry to indicate an error in a data memory access operation, snoop circuitry for snooping memory access operation in said data memory access circuitry, synchronising means for synchronising snooped data memory access addresses with respective program counts for the instructions associated with said access addresses, memory mapped storage circuitry responsive to a data memory access error to indicate the data memory address associated with the error, whereby the emulator circuitry may use the data memory address in a subsequent operation to obtain from the synchronising means the specific program count associated with the memory access operation in which the error occurred.

Abstract: A method for forming in monolithic form a DRAM-type memory, including the steps of forming, on a substrate, parallel strips including a lower insulating layer, a strongly-conductive layer, a single-crystal semiconductor layer, and an upper insulating layer; digging, perpendicularly to the strips, into the upper insulating layer and into a portion of the semiconductor layer, first and second parallel trenches, each first and second trench being shared by neighboring cells; forming, in each first trench, a first conductive line according to the strip width; forming, in each second trench, two second distinct parallel conductive lines, insulated from the peripheral layers; filling the first and second trenches with an insulating material; removing the remaining portions of the upper insulating layer; and depositing a conductive layer.

Abstract: Integrated circuitry including a clock circuit powered by a first power supply and a secondary circuit powered by a second power supply. The secondary circuit includes a control signal output for supplying a control signal to the clock circuit and a clock data output for outputting new clock data to the clock circuit.

Abstract: A method of manufacturing a bipolar transistor in a single-crystal silicon substrate of a first conductivity type, including a step of carbon implantation at the substrate surface followed by an anneal step, before forming, by epitaxy, the transistor base in the form of a single-crystal semiconductor multilayer including at least a lower layer, a heavily-doped median layer of the second conductivity type, and an upper layer that contacts a heavily-doped emitter of the first conductivity type.

Abstract: A lateral MOS transistor including a gate and drain and source regions of a first conductivity type formed in a substrate of a second conductivity type connected to a first power supply, wherein a doped buried layer of the first conductivity type extends under said drain region and under a portion of the gate, the buried layer being connected to the gate via a one-way connection.

Abstract: An inductance formed in an integrated circuit chip, formed of a plurality of parallel conductive lines, of optimized width, each conductive line being formed in the thickness of at least one insulating layer, these lines being interconnected by at least one perpendicular conductive segment.

Abstract: A valve, such as a gate valve, includes a housing having a fluid conduit and defining a valve seat and a support surface, a seal plate, a counter plate, an actuator for moving the seal plate and the counter plate between an open position and a closed position, and a coupling mechanism operatively coupled between the seal plate, the counter plate, and the actuator. The seal plate is in sealed engagement with the valve seat, and the counter plate is in engagement with the support surface in the closed position. The coupling mechanism retracts the counter plate from the support surface subsequent to retraction of the seal plate from the valve seat as the valve is opened.

Abstract: The present invention relates to a conductive line on an integrated circuit. The integrated circuit includes an insulating layer in which is formed several grooves of predetermined width. The conductive line includes a first interconnection layer having a first thickness and a second interconnection layer having a second thickness. The predetermined width is greater than twice the greatest of the two thicknesses, and smaller than twice the sum of the thicknesses.