Abstract: A protective tape is applied to the device side of a wafer (to protect it during an operation to grind the back side of the wafer) after the surface has been prepared to present only sloping surfaces to the tape. This profile prevents the otherwise sharp edges of the holes for the bonding pads from cutting into the adhesive of the tape and causing adhesive particles to remain on the wafer surface after the tape has been removed. Particles of resist can interfere with attaching wires to the bonding pads. The tape receiving surface of the wafer is commonly formed by a passivation layer and by bonding pad sites that are exposed through holes in the passivation layer. These sloping profiles can be formed by giving a sloping profile to the holes in the photoresist before the holes are etched. Alternatively the holes can be etched suitably wider at the top than at the bottom.

Abstract: A wafer for testing a manufacturing process for vias has a large number of vias (millions) formed into strings that have an open circuit resistance if the string contains a defective via and have a resistance of a few thousand ohms if the string is good. A multiplexor circuit is formed on the test wafer and scans the via strings and produces a binary output denoting that the addressed string is good or defective. The addresses are generated off the wafer by a compute and a defective string is readily identified.

Abstract: Cleaning apparatus for the wheels of a car used in a semiconductor manufacturing plant has a pair of endless belts that carry a dust trapping material on their outer surfaces. The belts turn against a wheel and thereby remove the dust.

Abstract: After identifying characters are written on the wafer surface 16 as a pattern of small holes 19 formed with a laser in the wafer I.D. stage of a semiconductor manufacturing process, the wafer surface in the region of the I.D. is polished to break loose deposits of silicon 20 that are left on the wafer surface and the region is then washed. The process prevents semiconductor material deposited on the wafer surface during the laser operation from later breaking off as hard particles that can scratch the surface of the wafer.

Abstract: A cleaning station for cleaning parts from apparatus that itself uses a water spray to clean a toxic gas. The cleaning station has a tray and a sink for holding a part to be spray cleaned and the sink is connected to drain the spray water into the drain system of the gas cleaning apparatus.

Abstract: A system for pumping resist to a wafer coating machine includes a line that returns a selected proportion of the resist entering the resist pump to the resist supply tank. The return line to the tank is connected to the pump outlet at a higher point than the pump outlet to the wafer coating machine, and the resist that is returned to the tank carries substantially all of the bubbles that are carried in the resist entering the tank. The bubbles are removed from the resist in the tank and the resist can be used normally.

Abstract: A hand operated tool for picking up a semiconductor wafer includes a vacuum cylinder with a piston. The user first pushes the piston to its forward most position against the force of a spring and a catch mechanism locks the piston in this position. Later, the user presses a button to release the catch mechanism and allow the piston to move to its rear most position in response to the force of the spring. The motion of the piston creates a suitable vacuum in the front part of the cylinder. A vacuum head is attached to the forward end of the cylinder. It has a generally square flat surface with sides about one third the diameter of a wafer. The user positions this surface in contact with a wafer and then pushes the button to releases the piston and apply a vacuum to grasp the wafer. The user moves the wafer to its destination and then presses a second button to allow air to enter the vacuum side of the cylinder and thereby release the grasp on the wafer.

Abstract: An improved filter system, particularly for the furnaces of a semiconductor manufacturing plant, has a standby filter and a piping system for connecting it momentarily in parallel with a normally used filter of one of the furnaces. A system of valves permits the normal filter to be isolated from its furnace so that it can be allowed to cool and then removed and replaced. The filter system avoids the problem that a standby filter is otherwise required for each furnace or that the replacement can not be made at a convenient time.

Abstract: A CMOS inverter has two p-channel FETs connected in series between V.sub.DD and the inverter output node, an upper FET connected to V.sub.DD and a lower FET connected to the output node. The gate of a upper FET and the gate of the inverter n-channel FET are connected to the circuit input through a series FET that protects the gate oxide of these FETs by turning off if a high voltage appears at the circuit input. The circuit is useful as a buffer that receives binary voltages that may be higher than the binary voltages of the circuits of the same chip. The gate of the upper p-channel FET is connected to the input and turns off fully to block a leakage current that would otherwise flow when the n-channel FET is turned on but the lower p-channel FET is left partly conducting by the voltage drop across the series FET.

Abstract: An FET with a lightly doped drain is connected between an input/output pad and ground and is protected from ESD at a pad by a structure that includes a resistor formed by the process step for the lightly doped drain. The resistor adjoins and interconnects a diffusion underlying the pad and the diffusion for the drain of the FET. A parasitic bipolar transistor is formed by the pad diffusion, the source diffusion for the FET, and the intervening substrate. When an ESD voltage appears at the pad, the FET conducts in circuit with the resistor and the voltage drop across the resistor helps to protect the FET and to turn on this parasitic bipolar transistor (in preference to a parasitic bipolar transistor otherwise formed by the FET) and thereby hold down the ESD voltage at the pad and at the drain of the FET. The FET and resistor can be formed as a number of parallel connected FETs and resistors located symmetrically on opposite sides of the pad diffusion. Protection for an input inverter circuit is also provided.

Abstract: A circuit for turning off an indicator light operates in two phases that provide a first rapid discharge phase and a second slow discharge phase. This sequence dims the light in a visual approximation of the exponential dimming that occurs with lights that operate with power supplies that have capacitors that give a slow turn off. The preferred light is an electroluminescent element that will be called a glow-effect capacitor which stores sufficient charge for slow turn off. When a switch associated with the light is opened, an FET turns on to discharge the capacitor rapidly to a selected voltage. This FET is then turned off and other components discharge the capacitor slowly. The switching signal for this FET is formed as a logic function of the switch position (open or closed) and the occurrence of the selected voltage level on the glow-effect capacitor.

Abstract: A cushioned holder for a cylindrical container for a semiconductor wafer is formed of a stack of layers of a cushioning material that each have a rectangular opening for receiving the container; the layers are spaced from the box by several absorbers having a mirrored pyramidal frustum shape. The shape is easy to manufacture and it provides improved cushioning without increasing the space occupied by the layers.

Abstract: A tablet system has an improved operation for saving power. During a digitizing period, the tablet supplies power to resistive sheets that produce analog pen position signals and to the sample and hold circuit and the analog to digital converter that operate on these signals. During a wait state, power is removed from these components and a separate circuit detects contact with the tablet surface by a pen. A pen activity circuit that uses less power is also disclosed. The pen activity detecting circuit has a resistor in circuit with the two resistive sheets. This resistor and associated circuits are independent of the normal path for signals that denote pen position and thereby allow these components to be turned off. When the pen is positioned on the tablet surface, the two resistive sheets are brought into contact in the normal way for detecting the pen position. During a period of pen inactivity, this contact produces a current in the resistor.

Abstract: A holder for samples to be analyzed in a spectrometer is made of a polymer to avoid introducing metal contaminates into the test from the usual metal holder. The preferred polymer is polyvinylidenefluoride (PDVF). The holder uses less expensive polymers for components that do not require the properties of PDVF, and it is constructed to permit replacing parts made of PDVF that have become damaged.

Abstract: An improved ESD protection circuit of the type having a field transistor connected as a clamp between ground and a pad to be protected and an FET trigger circuit that is connected between ground and a node where the protected circuits are connected. A resistor interconnects the pad and the node. The trigger FET turns on when a high ESD voltage causes avalanche breakdown and charge carriers from the trigger FET turn on the field transistor clamp. Before the field transistor clamp turns on, oxide breakdown in the gate oxide of the FET occurs. A resistor is connected between the gate electrode and ground to limit the current through the oxide during the time for the avalanche to develop and for the clamp to turn on.

Abstract: An FET is connected between ground and a pad to be protected from an ESD voltage, and when an ESD voltage appears at the pad the drain-channel junction breaks down and produces hole-electron pairs that turn on a parasitic bipolar transistor which clamps the voltage at the pad. A resistor connects the gate of the FET to ground. As the ESD voltage rises at the pad, the gate to drain capacitance charges in circuit with the resistor. The voltage across the gate oxide rises slowly enough that the FET is enabled to produce hole-electron pairs for turning on the bipolar transistor before the oxide voltage has reached a value that might damage the gate oxide.

Abstract: A buffer memory system provides independent memory blocks, each with independent addressing and data paths, for a processor and input and output devices. The processor can configure the data paths so that an input device can initially supply data to a first memory block. The processor can then assign a second block for input and operate on the data in the first block. The processor can store the results of the process in a third block that has been assigned to an output device. The memory blocks and the associated data paths can paired for operating with a processor with a wider data bus.

Abstract: A station for coating a semiconductor wafer with a photoresist is provided with a detector for bubbles that may occur in the resist that is supplied to the wafer. The resist is carried to the coating apparatus by a plastic tube. A commercially available capacitance detector is positioned to detect the dielectric constant of the combination of the tube, the resist, and any bubbles in the resist. The dielectric constant of the bubbles is lower than the dielectric constant of the resist, but the difference is not sufficient for detecting the bubbles with the capacitance detector alone. A metal backing plate is located on the side of the tube opposite the detector and enhances the operation of the detector sufficiently to detect bubbles of various sizes.

Abstract: A threshold circuit that uses capacitors to form a weighted sum of its inputs uses a two stage capacitor structure. The two stages form a compact structure that increases the number of input signals that can be handled and increases the flexibility in assigning the weights to the input signals. Capacitor electrodes for the input signals are arranged in two sets and the electrodes of each set are electrostatically coupled to first and second electrodes. Third and fourth electrodes, which extend from the first and second electrodes respectively, are electrostatically coupled to a unitary structure of fifth and sixth electrodes where their voltages are summed. The fifth and sixth electrodes are conductively connected to the gate of an FET threshold circuit that responds to the weighted and summed input signals.

Abstract: A flat panel display has an improved selection circuit for scanning row lines while data signals are applied to column lines for writing a selected image onto the pixel forming elements along the selected row line. The number of row lines, N, is chosen to be the product of two numbers, P and Q and preferably N is a perfect square. A first timing circuit provides Q number of non-overlapping timing signals that each have P narrow clock pulses each of a width for writing data into one row the display; it also provides P number of non-overlapping timing signals that each have clock pulses with a width of Q write operations. For each row line of the display, the selection circuit has an AND logic circuit that responds to one wide pulse clock line and one narrow pulse clock line to connect the row line to a voltage to enable the pixel forming elements to turn on in a write operation.