Abstract: A structure and method is provided for forming a contact plug in a contact hole in a dielectric layer on a semiconductor substrate. A polysilicon spacer is formed on the sidewalls and bottom of the contact hole. A metal, such as titanium, is deposited on the sidewalls and bottom of the hole and on the dielectric layer. The substrate is heated to form a metal silicide layer, such as TiSi.sub.x, and a metal nitride layer, such as TiN, on the side-walls and bottom of the contact hole. Any remaining metal layer and metal nitride layer formed in the heating process is removed. This leaves the titanium silicide layer on the contact hole walls. Tungsten is deposited to fill the contact hole where the metal silicide promotes the nucleation of the tungsten. In a preferred embodiment, to further promote nucleation of the tungsten, a second metal nitride layer is formed on the surface; of the metal silicide layer just prior to tungsten deposition.

Abstract: An improved method and structure for producing electrically programmable read only memory devices (EPROM's) and flash EPROM's having dual sidewall floating gates is provided. A conformal polysilicon layer is formed over a masking line with vertical sidewalls. The conformal layer is anisotrophically etched to form dual floating gates on the sidewalls of the masking line. The masking lines is removed. Source and drain regions are formed in-between and on either side of the dual gates. An insulating layer is formed over the dual gates and substrate surface. A control gate is formed over the dual gates. Word lines and other electrical contracts are formed to complete the EPROM or flash EPROM device.

Abstract: A method for forming a metal contact in a self aligned contact region over a impurity region in a substrate which comprises forming a doped polysilicon layer over the device surface except in a contact area. A thin polysilicon barrier layer and a metal layer, preferably tungsten, are then formed over the polysilicon layer and the contact area. The resulting metal contact has superior step coverage, lower resistivity, and maintains the shallow junction depth of buried impurity regions.

Abstract: A memory cell layout and method of forming a 6 transistor SRAM memory cell that achieves a reduced cell area using uncomplicated fabrication steps. In one embodiment, a six transistor (6/T) SRAM cell has two horizontal thin-film transistor (T5, T6) as load transistors, two transfer transistors (T1, T2), two latch transistors (T3, T4) and two current nodes (38, 40). In this structure all six transistors are formed in the substrate and a single polysilicon layer.