Abstract: The method allocates a demanded amount of power to a plurality of power output apparatus, each power apparatus having characteristic curves associated therewith, and the total power outputted from the plurality of power apparatus results in a minimum cost for generating the power. Each boiler is allocated a quantity of waste fuel to be used in the generation of power, the quantity of waste fuel to be a predetermined total over a predetermined time period. Data is entered for each of the power apparatus into a controller. Optimal solutions are generated for all valid possible output power demands using an optimization by parts technique within bounds of each power apparatus. The solutions indicate the portion of power each power apparatus is to supply to provide the total power demanded at minimal cost. The solutions are stored in tables within a storage unit of the controller.

Abstract: The method allocates a demanded amount of power to a plurality of power output apparatus, each power output apparatus having an emissions curve associated therewith, such that each of the power output apparatus supplies a portion of the demanded power, and the total power outputted from the plurality of power output apparatus results in a minimum amount of emissions. Data is entered for each of the power output apparatus into a controller. Optimal solutions are generated for all valid possible output power demands using an optimization by parts technique within output power bounds of each of the power output apparatus. The solutions indicate the portion of power each power output apparatus is to supply to provide the total power demanded at minimal emissions output. The solutions are stored in tables within a storage unit of the controller. Upon receipt of a demand for power, a search is performed of the solution tables to obtain the amount of power each power output apparatus is to supply to meet the demand.

Abstract: The method guarantees the integrity of a process control systems display in an open system windows environment. The process control system includes an interface apparatus to at least one foreign system, and receives display information such that the display information from the foreign systems and the display information from a network of the process control system are displayed on a display unit of the process control system in a windows format in response to control information from the interface apparatus. The interface apparatus transmits the display information of the foreign systems to a display generator unit via a first input channel of the display generator unit. Control information is also transmitted to the display generator unit via the first input channel to command a display format to the display generator unit of the display unit. The display format includes a plurality of windows, one of the windows being a control view.

Abstract: The time of a second network is synchronized to a first network, each network having an independent timing subsystem, includes the following steps. The first network sends a first message to the second network, the first message being uniquely identified as a sync message. A first relative time is obtained within the first network of when the first message is transmitted. When the first network recognizes that the first message was sent, a second relative time is obtained to send a second message to the second network containing a real time of the first network that the first message was sent. The second network obtains a third relative time within the second network of when the first message is received. The real time of the first network contained in the second message is associated to the third relative time of the second network, thereby synchronizing the time of the second network to the time of the first network.

Abstract: A memory unit, made up of a plurality of BY-4 memory devices, has a plurality of computer words, each computer word including a predetermined number of data bits and a predetermined number of check bits. An error detection and correction (EDAC) apparatus interfaces with the memory unit for detecting and correcting a single bit error of the computer word, detecting a two bit error of the computer word, and detecting all two, three, and four bit errors of a single memory device. Matrix logic generates the check bits from preselected participating data bits of the data bits of the computer word being fetched. Compare gate logic compares check bits from the memory unit to corresponding check bits generated by the matrix logic to generate syndrome bits.

Abstract: A computer system, having external peripherals, includes an operating system and application packages residing therein. Data exchange logic permits an outside application package (generated by a third party to perform a predefined application function in a general purpose computer environment) to be integrated into the computer system. A data file containing information for making the necessary data available to the outside application package in the computer system is generated off-line. When the outside application package is executing in the computer system and it is desired to obtain the necessary data, a first package is accessed. The first package utilizes information contained in the data file to generate commands to obtain the necessary data. Information of the data file includes source information of the necessary data internal to or external to the computer system. If, however it is desired to output results of the predefined application function, a second package is accessed.

Abstract: The apparatus detects a difference of frequency between a first signal having a first frequency and a second signal having a second frequency, the first and second signals being digital signals. A phase shifter shifts the first signal such that the first signal and the shifted first signal are sufficiently out of phase to keep the rising and falling edges of the two signals from occurring at the same time thereby avoiding subsequent simultaneous triggering conditions and jitter conditions between the first and second signal. A first gate samples the second signal by the shifted first signal to output a first sampled signal. A second gate samples the second signal by the first signal to output a second sampled signal. A sample gate samples the first sampled signal and the second sampled signal to generate a difference signal, the difference signal containing a difference value of the frequency difference between the first and second signal.

Abstract: In a computer system having fault recoverable capability, there is included a first and second data processing unit (DPU), wherein each of the first and second DPU is executing the same task essentially in parallel. Each DPU comprises a processor, a memory and a protected memory. The protected memory stores system data, such that the system data stored in the protected memory is immune from transient conditions. Also included is a monitor, which is operatively connected to the monitor of the other DPU. The monitor detects the occurrence of an upset to reinitialize the DPU, the DPU being reinitialized to a condition just prior to the occurrence of the upset thus avoiding utilization of any potentially erroneous data, and thereby permitting the DPU to return to its normal processing with valid data.

Abstract: The method allocates a demanded amount of power to a plurality of power output apparatus, each power output apparatus having a cost curve associated therewith, such that each of the power output apparatus supplies a portion of the demanded power, and the total power outputted from the plurality of power output apparatus being optimally cost efficient. Data is entered for each of the power output apparatus into a controller. Solutions are generated for all possible output power demands using an optimization by parts technique within output power bounds of each of the power output apparatus. The solutions indicate the portion of power each power output apparatus is to supply to provide the total power demanded at the optimal cost efficient. The solutions are stored in tables within a storage unit of the controller. Upon receipt of a demand for power, a search is performed of the solution tables to obtain the amount of power each power output apparatus is to supply to meet the demand.

Abstract: A controller of a control system, which operates as a master, has a slave input/output processor (IOP) connected thereto which communicates with at least one device of a predetermined type, and a backup slave IOP connected thereto of the same type as the slave IOP, the slave IOP operating as a primary IOP to the device. A method for providing backup to the slave IOP by the backup slave IOP comprises the steps of loading the backup slave IOP with the same data base as the slave IOP. The backup slave IOP eavesdrops on all communications from the controller to the slave IOP. When a write command is communicated to the slave IOP, the backup slave IOP taps the data from the bus and updates its data base. If the command is not a write command, ignores the communication. When a fault is detected by either the slave IOP or the backup slave IOP, the detection of the fault is communicated to the other IOP.

Abstract: A primary slave IOP, upon detecting an error, verifies the availability of a secondary slave IOP, and then sets an output control signal to indicate backup is requested. The primary slave IOP then takes itself out of being the primary. A secondary slave IOP, sensing that the output control signal from the other IOP has been set, assumes the roll of the primary slave IOP. A master controller, detecting an error with the primary slave IOP, interrogates the primary and secondary slave IOPs for a status input, and then arbitrates between the first and second IOP to determine the IOP that is to take on the primary role. Finally the master controller awards the more operational IOP the role of the primary slave IOP, thereby completing the failover operation.

Abstract: An integrated circuit comprising a substrate. The substrate comprises a semiconductor material and has a first surface. The circuit further comprises a layer of metalization interconnects over the first surface, each interconnect having a width. A first thin film layer comprising a dielectric barrier material is deposited directly onto the first layer of metalization interconnects. A second thin film layer comprising a dielectric passivating material is deposited directly onto the first thin layer of dielectric barrier material. A via is formed in the two thin film layers over a first metalization interconnect protruding into the via. The first metalization interconnect has a width less than the width of the via. A second metallization interconnect is connected to the first metalization interconnect in the via.