Patents Represented by Attorney William W. Cochran
  • Patent number: 7082585
    Abstract: Disclosed is a method of analyzing an integrated-circuit system that is accurate for high frequency analysis and can predict problems at high frequencies that do not occur when the circuit is used at lower frequencies.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: July 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: Frantisek Gasparik, Joseph J. Brehmer
  • Patent number: 7082557
    Abstract: A high speed, two-way serial interface with a scrambler and de-scrambler may be tested by sending a single word repeatedly through the scrambler to create a pseudo-random sequence. The pseudo-random sequence is then passed through the transmitter and looped back through the receiver of the serial interface. The pseudo-random sequence is then descrambled and compared to the input word. Since the input sequence is only a single word rather than a series of words, the comparison is very simple and capable of being performed within the serial interface itself without the need for external test equipment.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: July 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: Steven Schauer, Kevin Campbell
  • Patent number: 6898767
    Abstract: Disclosed is a method for converting a SPICE format circuit description to a standard cell HDL netlist, such as Verilog, allowing simulation and verification in HDL format. SPICE elements may be converted to circuit functions and corresponding standard cells are then selected. The SPICE netlist is employed to define timing paths. Timing information from SPICE simulation is correlated with timing characteristics of the standard cells and a standard delay file is produced such that, when applied to the standard cells, timing approximates that of the SPICE simulation. The present invention may also employ SPICE to Verilog conversion wherein a SPICE netlist is converted to a Verilog standard cell netlist. Timing information from SPICE simulation is correlated with timing characteristics of the standard cells in the Verilog netlist and a standard delay file is produced such that, when applied to the standard cells, timing approximates that of SPICE simulations.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: May 24, 2005
    Assignee: LSI Logic Corporation
    Inventor: Duncan Halstead
  • Patent number: 6885078
    Abstract: A circuit isolation technique that uses implanted ions in embedded portions of a wafer substrate to lower the resistance of the substrate under circuits formed on the wafer or portions of circuits formed on the wafer to prevent the flow of injected currents across the substrate. The embedded ions provide low resistance regions that allow injected currents from a circuit to flow directly to a ground potential in the same circuit rather than flowing across the substrate to other circuits. High energy implantation processes on the order of 1 MeV to 3 MeVs can be used to implant the ions in embedded regions. Multiple energy levels can be used to provide thick embedded layers either prior to or after application of an epitaxial layer. Various masking materials can be used to mask the isolation regions during the implantation process, including hard masking materials such as silicon dioxide or silicon nitride, poly-silicon or an amorphous silicon layer, and a photoresist layer.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: April 26, 2005
    Assignee: LSI Logic Corporation
    Inventors: Donald M. Bartlett, Gayle W. Miller, Randall J. Mason
  • Patent number: 6861864
    Abstract: A test vehicle a system and method for evaluating an interconnect module manufacturing process while dynamically testing performance with high-speed operational frequencies is disclosed. An interconnect module designed at many of the manufacturing process limits offers complete and fast failure analysis so that manufacturing defects can be quickly located and the process improved. Failure analysis, particularly on 90 nm technologies and beyond is becoming extremely difficult. At-speed testing is also becoming very important to the yield and reliability of products. This invention incorporates a self-timed speed circuit that can detect subtle resistive faults and also show the exact location in the array where the speed fault occurred based on test program datalogs from scan flip flops.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: March 1, 2005
    Assignee: LSI Logic Corporation
    Inventor: Richard Schultz
  • Patent number: 6781151
    Abstract: A test vehicle for evaluating a manufacturing process for integrated circuits comprises a staircase of vias and traces arranged for maximum test coverage. The staircase may be combined with several functional cells to produce circuits that exercise many interconnections that may be designed at the minimum design parameters of manufacturing process. The accessibility of many testing methods allows an engineer to quickly find root cause failures and thus make improvements to the manufacturing process.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: August 24, 2004
    Assignee: LSI Logic Corporation
    Inventors: Richard Schultz, Steve Howard
  • Patent number: 6747349
    Abstract: A rectangular termination ring for a power distribution mesh is placed on the upper two layers of an integrated circuit and may be placed over some I/O circuitry. The strapping connecting the bonding pads to the termination ring are placed on upper levels of the integrated circuit, minimizing the via requirements and freeing space for additional circuitry. Further, the termination ring may be adapted to work in conjunction with L-shaped, as well as other power distribution meshes.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: June 8, 2004
    Assignee: LSI Logic Corporation
    Inventors: Maad Al-Dabagh, Thomas Antisseril, Bo Shen, Prasad Subbarao, Radoslav Ratchkov
  • Patent number: 6728238
    Abstract: A system for dynamic allocation of voice and data channels in a time division multiplexed telecommunication system is disclosed. Multiple time division multiplexed lines are provided between a Teleco central office and a number of remote terminals. The time division multiplexing provides multiple channels on each of the multiple DSL lines so that multiple POTS devices can be connected to a single remote terminal. In addition, the remote terminal provides a high speed data port for connection to a data device such as a computer, a router, a bridge, a switch or other similar devices. The multiple TDM channels on each DSL line are allocated so that all of the channels are available for transmission of voice signals and all of the remaining open channels are available for the transmission of data signals.
    Type: Grant
    Filed: December 17, 1999
    Date of Patent: April 27, 2004
    Assignee: Remote Switch Systems, Inc.
    Inventors: Gary E. Long, Eric M. DeLangis
  • Patent number: 6712479
    Abstract: The present invention includes maintaining the region of the proximal lens of a laparoscope at greater than ambient temperature in order to prevent fogging during use. Heating is accomplished using commercially available chemical heat packs generally used for heating boots or gloves, or by using electrically powered heating tape. The invention differs from other anti-fogging devices, which either immerse the distal lens region of the laparoscope in a warm fluid or treat this lens with anti-fogging solutions, in that above-ambient temperature is continuously maintained throughout the laparoscope, since it is known that a cool laparoscope fogs when placed in the vicinity of warm, wet patient tissue.
    Type: Grant
    Filed: April 22, 2000
    Date of Patent: March 30, 2004
    Assignee: Innovative Surgical Technology, Inc.
    Inventors: Michael R. Seitzinger, David Platts
  • Patent number: 6707709
    Abstract: A static random access element is comprised of three transistors and two resistors. Two transistors have their gates and drains cross connected to the respective drains and gates of the opposite transistor. Two resistors make the connection from a power supply to the drains of each of the two transistors. A first control line is connected at the junction of the two resistors. The source of a third transistor is connected to the gate of one of the first transistors and the drain of the third transistor is connected to a second control line and a power supply. The gate of the third transistor is connected to a third control line. The three transistor SRAM cell is more compact and requires fewer control lines than typical SRAM cells.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: March 16, 2004
    Assignee: LSI Logic Corporation
    Inventor: Jeffrey Lussenden
  • Patent number: 6704810
    Abstract: Persistent reservations may be processed on an as-needed basis after a power cycle sequence. A computer storage device may have persistent reservations for various volumes that are to be deleted after a power cycle but before accepting any reservation I/O requests for those volumes. After a start up sequence, the device comes on-line prior to deleting the required registrations. Prior to the first reservation I/O request for the particular volume, the registrations are processed for that volume and the necessary registrations are deleted.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: March 9, 2004
    Assignee: LSI Logic Corporation
    Inventors: Stanley E. Krehbiel, Jr., David J. Ulrich
  • Patent number: 6701495
    Abstract: Accurate models of the contact region of an integrated circuit resistor are created in a single function. The function incorporates many contact geometries into a single function that cannot otherwise be represented by a closed form solution. A method of creating the function uses regression over the simulation results for many combinations of input variables. The function may use the contact resistance, metal trace resistance, and resistive area resistance as inputs to calculate the resistor contact region resistance.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: March 2, 2004
    Assignee: LSI Logic Corporation
    Inventor: Russell E. Radke
  • Patent number: 6693989
    Abstract: An apparatus and method for the generation of ultrabright multikilovolt x-rays from saturated amplification on noble gas transition arrays from hollow atom states is described. Conditions for x-ray amplification in this spectral region combine the production of cold, high-Z matter, with the direct, selective multiphoton excitation of hollow atoms from clusters using ultraviolet radiation and a nonlinear mode of confined, self-channeled propagation in plasmas. Data obtained is consistent with the presence of saturated amplification on several transition arrays of the hollow atom Xe(L) spectrum (&lgr;˜2.9 Å). An estimate of the peak brightness achieved is ˜1029 &ggr;·s−1·mm−2·mr−2 (0.1% Bandwidth)−1, that is ˜105-fold higher than presently available synchotron technology.
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: February 17, 2004
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Charles K. Rhodes, Keith Boyer
  • Patent number: 6680629
    Abstract: A long channel transistor and a shorter channel transistor operate in conjunction to drive an output node. The long channel device is first activated by a drive signal and the drive signal is input to a delay element that then activates the shorter channel device. By enabling the long channel device first, hot carrier injection effects are reduced. Employing two transistors that are sized to operate in different voltage ranges reduces surge current. The two-transistor configuration of the present invention occupies less area than a single long channel device with similar drive capabilities.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: January 20, 2004
    Assignee: LSI Logic Corporation
    Inventors: Andrew M. Rankin, Jason Hoff, Ken Szajda
  • Patent number: 6676837
    Abstract: The present invention is a solar powered aeration system that incorporates a battery. The device can be used for improvement of water bodies for use in aquaculture systems, reservoirs, water storage tanks, fish tanks, artificial ponds and lakes, and the like. The device does not require connection to the electrical power grid and may be used in any location. Further, the device can be used during periods of low oxygen content, which is typically the period of day just before sunrise. Additionally, the device uses a laminar column of water to enhance circulation of the water body. Increased efficiency can be obtained by matching the diffuser to the pump size, which is important in solar powered applications.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: January 13, 2004
    Inventor: Jimmie A. Keeton, Jr.
  • Patent number: 6675139
    Abstract: A method for designing and mapping a power-bus grid in an integrated circuit. A floor plan is created by mapping wire segments of the power-bus grid to various metal layers of the IC core. Power zones which specify the current consumption of analog, digital, and memory block regions are also mapped to the IC core. A netlist of the floor plan design is generated and simulated, with the simulation returning current density and a voltage drop values in the wire segments with respect to the power zones. Calculated current density and voltage drop values are analyzed using a color map to indicate the current density and voltage drop levels of the wire segments. Power-bus wire segments are displayed in colors matched to the current density and voltage drop levels in the color map, helping the designer identify potential electromigration and voltage drop problems. The floor plan design can be modified if the calculated density and voltage drop values indicate potential electromigration or voltage drop problems.
    Type: Grant
    Filed: March 16, 1999
    Date of Patent: January 6, 2004
    Assignee: LSI Logic Corporation
    Inventors: Mark W. Jetton, Richard A. Laubhan, Richard T. Schultz
  • Patent number: 6671776
    Abstract: A system and method for dynamically generating the topology of a storage array network by linking information concerning hosts and clusters along with information about host port adapters. Namely, each host identifies itself to all controllers and provides information in a command that allows the controller to know which host and cluster, if applicable, is associated with the host port adapter through which the command was issued. In addition, the topology is automatically updated anytime there is a change on the network such as a new device was added or a host port adapter was replaced.
    Type: Grant
    Filed: January 24, 2000
    Date of Patent: December 30, 2003
    Assignee: LSI Logic Corporation
    Inventor: Rodney Allen DeKoning
  • Patent number: 6667825
    Abstract: Electrochemical synthesis of conjugated polymers in ionic liquids, achievement of electroactivity and electrochroism of conjugated polymers in ionic liquids, and the use of the resulting conjugated polymers for the fabrication of electrochromic devices incorporating ionic liquids as electrolytes are described.
    Type: Grant
    Filed: January 3, 2002
    Date of Patent: December 23, 2003
    Assignee: Santa Fe Science and Technology, Inc.
    Inventors: Wen Lu, Benjamin R. Mattes, Andrei G. Fadeev, Baohua Qi
  • Patent number: 6648064
    Abstract: An active heat sink uses a liquid coolant to transfer heat from a hot zone to a cool zone. The liquid coolant is propelled using a motor comprised of a plurality of external coils that are in magnetic communication with a plurality of magnets attached to a pump gear. The motor does not require any penetration of the liquid cavity. Further, the heat pump may have a temperature monitoring circuit to determine whether or not the pump should be activated.
    Type: Grant
    Filed: November 14, 2002
    Date of Patent: November 18, 2003
    Assignee: LSI Logic Corporation
    Inventor: George E. Hanson
  • Patent number: 6646864
    Abstract: Discloses is a protective case for an electronic device that has a touch screen. The touch screen is protected with a membrane adapted to the specific contour and profile of the electronic device and allows the user to use the touch screen interface with no shortcomings. The protective case is further adapted to allow infrared and other communication signals while the device is secured inside the case. Further, electrical connections can be made through the case without affecting the protection afforded the electronic device inside.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: November 11, 2003
    Assignee: Otter Products, LLC
    Inventor: Curtis R. Richardson