Abstract: A method for designing and mapping a power-bus grid in an integrated circuit. A floor plan is created by mapping wire segments of the power-bus grid to various metal layers of the IC core. Power zones which specify the current consumption of analog, digital, and memory block regions are also mapped to the IC core. A netlist of the floor plan design is generated and simulated, with the simulation returning current density and a voltage drop values in the wire segments with respect to the power zones. Calculated current density and voltage drop values are analyzed using a color map to indicate the current density and voltage drop levels of the wire segments. Power-bus wire segments are displayed in colors matched to the current density and voltage drop levels in the color map, helping the designer identify potential electromigration and voltage drop problems. The floor plan design can be modified if the calculated density and voltage drop values indicate potential electromigration or voltage drop problems.

Abstract: The present invention provides a method and apparatus for managing a large number of associated interconnects within an integrated circuit involving a modular approach to the macro cell layout. In a circumstance where a macro can be employed for multiple instantiations, and wherein such a design unique signals must be distributed to each instantiation, certain commonalities may exist which can be exploited to achieve a simple yet elegant approach facilitating the routing of these unique signal paths and premapping standardized contact points.

Abstract: A positionally based label application system includes a plurality of sensors which detect the pitch between the products to be labeled as well as the location of those products. A supply web bearing labels is caused to pass over a peel tip which feeds the labels into a nip point. This allows the labels to be precisely matched with products traveling at a very high rate of speed. The positional system determines a desired ratio of movement between the supply web and the product being conveyed, this ratio being based upon the detected pitch. In this manner, the supply web is allowed to move continuously, but at a slower speed than the products being conveyed, but still precisely matches labels to products.

Abstract: A method and system for real-time tracking of objects are disclosed. A region is repeatedly scanned providing a plurality of images or data sets having points corresponding to objects in the region to be tracked. Given a previously determined track for each object in the region, an M-dimensional combinatorial optimization assignment problem is formulated using the points from M−1 of the images or data sets, wherein each point is preferably used in extending at most one track. The M-dimensional problem is subsequently solved for an optimal or near-optimal assignment of the points to the tracks, extending the tracking of the objects so that a response to each object can be initiated by the system in real-time. Speed and accuracy is provided by an iterative Lagrangian Relaxation technique wherein a plurality of constraint dimensions are relaxed simultaneously to yield a reduced dimensional optimization problem whose solution is used to formulate an assignment problem of dimensionality less than M.

Abstract: A method of upstream communication over a linear broadband network includes the steps of generating an upstream baseband signal and modulating it onto an upstream wireless radio frequency carrier to produce a first upstream modulated carrier signal. The modulated carrier signal is transmitted wirelessly, received, and demodulated to reproduce the information integrity of the upstream baseband signal. The signal is then modulated onto an upstream linear broadband radio frequency carrier for transmission on the linear broadband network. Advantageously, noise that accumulates at the subscriber premises is removed from the upstream signal prior to presentation of the signal to the upstream path of the linear broadband network. A system for communicating over a linear broadband network includes network access interface devices coupled to the linear broadband network.

Abstract: Disclosed is a quantizer that uses optimum decision thresholds that are determined by the average of the optimum reconstruction levels of a detected signal in the presence of noise. The Lloyd-Max Quantizer is used to determine the optimum reconstruction levels yK using a minimum means squared error technique. Decision thresholds xK are therefore established at levels where influences of noise or other distortions are equally likely to occur between adjacent transmitted points. The present invention can be utilized in quadrature amplitude modulation (QAM) systems or any quantizer design that quantizes an analog signal.

Abstract: A system for generating correction factor data that is representative of the distortion characteristics of a cathode ray tube. The correction factor data is stored with a cathode ray tube to allow later alignment of a video signal, or can be provided on a storage medium or on a network. Distortion data, and resultant correction factor data is generated for a series of discrete physical locations on the cathode ray tube screen. In this manner, the entire screen surface can be utilized to align a video image. Maximum correctable distortion data is also generated in accordance with the present invention to provide exit criteria for cathode ray tube manufacturers. The exit criteria is based upon maximum correction factor data that can be generated to correct distortions.

Abstract: A SCSI-2-and-DMA processor that has on a single integrated circuit a SCSI-2 interface for a SCSI-2 data bus that is at least two bytes wide and a DMA interface for a system data bus that is at least two bytes wide. This integrated circuit has an set of control registers and an on-chip processor such that the transfers involving SCSI-2 data transfers involving data words that have a width of at least two bytes can be processed and completed without burdening the remainder of the system. Substantially all that is needed of the system processor is to down load a very compact control program and then transfers between this integrated circuit and system RAM. The on-chip processor allows chaining of random length blocks of contiguous address data by using a chain mode of transfer which also pairs up any odd residue with a portion of the first word of the next block in the chain using on-chip processing.

Abstract: A process is described for electrically interconnecting electronic devices located on a surface through one or more planar linking layers consisting of conductors and dielectrics. A three-step additive process is disclosed for forming each planar linking layer. The process may be repeated in order to form the multiple linking layers required for complex VLSI circuits. Each layer is formed by a three step process of applying a uniform dielectric, removing the dielectric where the interconnections, including vias and lines, are to be made and then selectively depositing a conductor to form the interconnections.

Abstract: A valve apparatus for controlling fluid flow comprising a substrate having a first aperture extending therethrough for defining a first fluid flow path; a beam having first and second terminal end portions mounted in fixed relationship with the substrate and having a bucklingly displaceable intermediate portion positioned in overlying relationship with the aperture for covering and uncovering the aperture for preventing or enabling fluid flow through the aperture; and a temperature control assembly for selectively controlling the temperature of the beam for selectively bucklingly displacing the intermediate portion of the beam for controlling fluid flow through the aperture.

Abstract: A Class-A complementary metal oxide semi-conductor (CMOS) operational amplifier is provided having an improved slew rate. The preferred embodiment of the invention utilizes a CMOS amplifier circuit and an external capacitor, which together exhibit relatively poor sourcing of current and hence a relatively low positive slew rate in response to an input signal being more positive than an output signal of the CMOS amplifier by a relatively large amount. The disparity between the input and output signals defines an error signal. The present invention also includes a supplemental output stage communicating with the amplifier circuitry and the external capacitor. The supplemental output stage is activated in order to supply additional sourcing current, thereby increasing the positive slew rate, when a relatively large error signal is present and is de-activated otherwise.

Abstract: Tape-automated-bonding (TAB) tape can be directly bonded (i.e., no "gold bumps" are needed) to aluminum bonding pads of integrated circuit devices, without contacting any other part of the integrated circuit device, by use of a process employing the herein disclosed parameters of ultrasonic energy, pressure, time, heat, and relative dimensions of the TAB tape.

Abstract: A board fixturing system is described for interfacing a printed circuit board having electronic devices at predetermined locations thereon to a probe plate having electrical contacts at predetermined locations. The fixturing system is mechanical and avoids the problems and limitations of the conventional vacuum fixturing systems. The fixturing system includes a unique conveyor system which is capable of staging one board while testing another, i.e. one board can be tested while another board is advanced toward the test fixture. A cassette system for the probe plates is also provided.

Abstract: A device for synchronizing the output test pattern signals of a test circuit with the clock signal of a device under test (DUT). The invention uses a programmable delay in the feedback loop of a phase locked loop system to adjust the phase of the test pattern signals to be synchronized with the clock of the device under test (DUT).

Abstract: Small and/or large defects in dielectric materials can be detected by bombarding one surface of the dielectric material with gas ions in order to impart a charge on that surface while the opposite surface is under the influence of an opposite charge. The dielectric material is then exposed to an indicator substance having an affinity for the charge of the gas ions and a tendency to congregate on regions of the dielectric materials which contain defects.

Abstract: A solution to accurately aligning a read-write head over a previously written data track on both a write protected and not write protected tape is disclosed. A control unit, preferably a programmed microprocessor, electronically provides a sequence of control outputs to move the tape and step the head to locate an edge of the tape. The control unit then moves the head a fixed distance to be over a selected data track. A threshold circuit controls the readout of data from the head of the tape in such a way as to improve edge find reliability.

Abstract: An in-circuit test device and method for testing transistors which are connected to various components on a printed circuit board. The present invention uses a fully automated system which provides a constant emitter current to bias the transistor to a predetermined level and prevents the transistor from going into saturation due to variations in the gain of different transistors. The collector lead and base lead are maintained at approximately ground potential so that the collector emitter voltage drop is maintained above the saturation voltage for transistors since the base emitter junction is biased by a constant emitter current placed in the emitter lead. Transistor gain is determined from the difference in two separate d.c. emitter currents which eliminates the effects of parallel impedence paths resulting from other components connected to the transistor on the printed circuit board.

Abstract: A device and process for programmatically generated and controlled in-circuit pin tests and gross functionality tests of operational amplifiers. The tests provide basic functionality verification of amplifier functions independent of other circuitry on the printed circuit board of which the operational amplifier is a component.

Abstract: A system and method for unambiguously determining the orientation of a semiconductor component in a circuit. The invention draws a predetermined biasing current from the signal node of a circuit that is sufficient to forward bias protection and/or parasitic diodes that exist between the ground pin and signal pin of the semiconductor component. Hence, if all of the semiconductors coupled to a signal node are connected in proper orientation, a voltage of -V.sub.D will be detected on the signal node. A voltage of approximately two diode voltage drops is applied to the power node so that the protection and/or parasitic diodes of a semiconductor placed in the circuit in reverse orientation will be forward biased to produce a voltage on the signal node equal to approximately one diode voltage drop. Missing components and bent pins do not affect the results of the test performed by the present invention.

Abstract: The system is for testing semiconductor components such as TTL components and CMOS components to determine whether the input, output and ground pins are conductively connected to a circuit, such as the circuit of a printed circuit board, and whether proper conductive paths exist between the connector pins and the ground pin through the semiconductor. This is accomplished by providing a current pulse on one terminal to generate a voltage drop across an inherent resistance of the component which is connected in series with the other terminal of the component and detecting the resulting voltage drop. The existence of the voltage drop indicates that both the input and output terminals, as well as the ground terminal, are properly connected to the printed circuit board.