Abstract: An information processing system includes an operation speed adjustable processor, and is adapted so that, with increase of operation speed of the processor, its performance is improved and power consumption is increased. The system comprises a scheduling unit for carrying out a processing to determine task of which processing should be executed at respective time points to shift control right to the task in accordance with the determination result, a power management unit periodically activated to carry out prediction of the power consumption of the processor and setting of operation frequency thereof, and a satisfaction degree evaluation unit activated in response to request from a scheduling module to evaluate the relationship between respective tasks and satisfactory services provided by them. Accordingly, it is possible to suppress operation frequency of the processor within the range that the satisfaction degree permits thus to carry out power saving.

Abstract: A data processing apparatus processes input data and outputs the processed data. The data processing apparatus includes a data processing section for processing the input data by a predetermined processing method and outputting the processed data, an input-data evaluation section for evaluating the input data, an output-data evaluation section for evaluating the output data, and a real-time learning section for controlling such that the processing method is learned in real time according to the evaluation results obtained by the input-data evaluation section and the output-data evaluation section and the data processing section processes the input data according to the learned processing method, and thereby, improves the output data every moment.

Abstract: A two-dimensional DCT system having a first calculation circuit, a rearrangement circuit, a second calculation circuit and a multiplier, and a two-dimensional IDCT system having a multiplier, a first calculation circuit, a rearrangement circuit, and a second calculation circuit. Each of these elements is adapted to receive data in a serial form, process the received data in its serial form, and output data in a serial form. As a result, serial-to-parallel converters and parallel-to-serial converters which may have a relatively large number of registers or hold circuits are not needed.

Abstract: A digital signal transmitting method, a digital signal receiving apparatus, and a recording medium which ensure the security of fee-charged software information. When an image providing predetermined services is transmitted, a band-compression coded digital video signal is given first-encryption processing and then the digital signal is further given encryption processing and transmitted. Therefore, double security can be added to the video signal and a digital signal transmitting method where its security is more firmly ensured can be realized.