Abstract: An apparatus and method for providing variable bandwidth in wireless air-link communication channels which allows a user of an end-user communicating device, e.g. a cellular phone, computer, facsimile, to request the allocation and aggregation of available air-link communication channels for the wireless transmission of messages to and from a mobile end-user communication subscriber unit, e.g. a cellular telephone or portable computer, so as to increase the speed of wireless transmission, wherein information transfer networks, channelized communication radios and microprocessors are typically employed for locating, reserving and aggregating available air-link channels and for transmitting messages between end-user communication devices, one being mobile.

Abstract: A data processing system includes a planar board having a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets or slots, each adapted to receive a selected one of a plurality of different and/or similar option cards. Each card contains (or is connected to) and controls a respective peripheral device; and each card is pre-wired with an ID value corresponding to its card type. Software programmable option registers on each card store parameters such as designated default (or alternate) address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in slot positions in main memory, one position being assigned to each slot on the board. Each slot position is adapted to hold the parameters associated with the card inserted in its respective slot and the card ID value.

Abstract: A program arrangement presently disclosed provides support within an operating system for a commonly used class of peripheral devices (e.g. mouse devices or, more generally, pointing devices). This arrangement effectively eliminates dependencies between device driver software associated with the supported device(s) and system (and/or application) software; so that device driver software can be created without extensive knowledge of the operating system and system software can be modified cost effectively without affecting the usefulness of existing device drivers. In this arrangement, device driving functions are assigned to two discretely separate program modules having a standardized interface. One module, included in the operating system, provides a device-independent base for coordinating device and system interaction. The other module is associated specifically and directly with supported devices, and can be created by programmers having little knowledge of the internal structure of the system software.

Abstract: Disclosed is a basic DCVS (differential cascode voltage switch) tree construct, which can be used as a uniform basis for constructing DCVS logic circuits, register-latch circuits and circuits which can be conditioned individually to function as either or both DCVS logic and register-latches. In addition to logic and load sections that may be identical to corresponding sections of prior art DCVS trees, this construct contains gating elements for providing unique functions of isolation, precharge support and latch input coupling. The isolation function is used to electrically isolate the logic and load sections from each other, so that each section can be made to operate in a mode which is independent of the other section. The precharge support function allows precharging of circuits in the logic section without involvement of the load section. The latch input coupling function allows signals to be applied to and latched in the load section from a source other than the respective logic section.

Abstract: Subject burst time division multiplex interface connects circuits which perform "layer 1 (L1)" line control functions relative to a data communication network with devices which perform "Layer 2 (L2)" link control functions relative to the same network (L1 and L2 defined by OSI Specifications of the International Standards Organization). The interface is characterized by presentation of bursts of readiness indicating pulses from the L1 circuit to the L2 device during each basic time division multiplex time slot. The pulses indicate readiness of the circuits for data bit exchange, and separate time overlapped bursts are sent to indicate readiness of the circuits to send and receive data bits. Each burst contains a varied number of pulses ranging from 0 to n (where n is greater than 2, and in the disclosed embodiment equals 8). The bursts are positioned in a window of time occupying a fraction of the slot interval close to the end of each slot.

Abstract: In a computer system having both peripherals having their own DMA channel arbiter and peripherals having no arbiter, a separate arbitration unit, controlled directly by the CPU, is provided to arbitrate on behalf of peripherals having no arbiter. The CPU can thus freely assign different arbitration levels to such peripherals, and can instruct the arbitration unit to simultaneously arbitrate on different arbitration levels or for two or more DMA channels.

Abstract: A "single-chip" integrated circuit device, useful in ISDN digital voice and data telephone applications, links plural channels of a data communication network with memory and CPU components of a data processing system. The device couples to the system via a bus that may be shared by other devices, and bidirectionally exchanges service information signals with the system CPU, and communication data signals with system memory. The service information includes device control information furnished by the CPU, and (channel and device) status information prepared by the device. The device contains multiple logic circuit units, operating in relative functional autonomy, and buffer memory units for storing service information and data. Units which interface to the network operate in synchronism with network communication processes. Units which interface to the system bus operate in asynchronous relation to network processes.

Abstract: A personal computer system according to the present invention comprises a system processor, a random access memory, a read only memory, and at least one direct access storage device. A direct access storage device controller coupled between the system processor and direct access storage device includes a protection mechanism for protecting a region of the storage device. The protected region of the storage device includes a master boot record, a BIOS image and a system reference diskette image. The BIOS image includes a section known as Power on Self Test (POST). POST is used to test and initialize a system. Upon detecting any configuration error, system utilities from the system reference diskette image, such as set configuration programs, diagnostic programs and utility programs can be automatically activated from the direct access storage device.

Abstract: A method and apparatus for rapid interconnection (hot plugging) peripheral device interface circuits to a computer bus is disclosed. The interconnections are completed using three sets of conductors in the sequence: common grounds, power from the bus and data lines. The time period between the interconnections is determined by the relative set back lengths of the conductors from the card edge and allows for stabilization of voltage and establishment of a stable high impedance state for the peripheral device controller circuits before the data lines are interconnected.

Abstract: An apparatus and method for loading BIOS stored on a direct access storage device into a personal computer system. The personal computer system comprises a system processor, a system planar, a random access main memory, a read only memory, and at least one direct access storage device. The first portion of BIOS initializes the system and the direct access storage device to read in a master boot record into the system from the direct access storage device. The master boot record includes a data segment and an executable code segment. The first BIOS portion vectors the system processor to execute the executable code segment of the master boot record. The executable code segment loads in the remaining BIOS portion from the direct access storage device into random access memory.

Abstract: An integrated data link control device (IDLC) interfaces between a host computer system and external channels in a communication network. The device contains multiple internal channels allocatable individually to interface to the external channels, each internal channel having internal buffer memory reserved to it for storing data signals handled by it. The device also includes facilities for selectively configuring groups of its internal channels into "extended channels", some of which are termed Hyper Channels. Channels in each extended channel group interface collectively and in time coordination to one external channel, presenting an effective bandwidth to the external channel which is greater than the bandwidth of any single internal channel.

Abstract: An apparatus and method for configuring a personal computer system for operation with a plurality of optional system consoles. A first non-volatile memory means stores present system configuration data. The present system configuration data is representative of the type of system console connected to the system. A diagnostic module accesses this configuration data for determining the operational validity of the system based upon a predetermined system configuration. The diagnostic module compares the present configuration data to the predetermined configuration. Based upon the comparison the diagnostic module modifies the operation of the system to communicate with the type of system console connected to the system.

Abstract: A computer system and method for operating a computer system capable of running in mutually incompatible real and protected addressing modes, in which programs written for one mode can be run in the other mode without modification. The BIOS assembles two different common data areas for the two modes, each inclusive of device block pointers, function transfer table pointers, data pointers, and function pointers. The common data area for the real mode is assembled first. To assembly the pointers for the protected mode common data area, the offset values from the real mode area ae copied directly, and then selector values are inserted whose physical addresses correspond to the segments of the corresponding pointers in the real mode area. The selector values are derived from a segment descriptor table.

Abstract: An apparatus and method for reclaiming a portion of random access memory in a personal computer system. The personal computer system comprises a system processor, a memory controller, a random access main memory, a read only memory, and at least one direct access storage device. The read only memory includes operating system microcode. The memory controller regulates communications between main memory and the system processor. In response to signals from the system processor, the memory controller can either execute the microcode out of the read only memory and recover main memory previously used to store the microcode, or disable read only memory, copy the microcode to main memory and execute the microcode out of main memory.

Abstract: An improved multi-channel direct memory access (DMA) controller for data processing systems provides adaptive pipelining and time overlapping of operations performed relative to communication channels. Registers and resources used to pipeline communication data and control signals relative to plural channels are adaptively shared relative to a single channel when command chaining is required relative to that channel. In command chaining a plural word command, termed a Device Control Block (DCB), is fetched from an external system memory via a bus having severe time constraints relative to potential real time requirements of the channels. Pipelining and time overlapping of channel operations, relative to plural channels, increases the effective rate of transfer at the bus interface to the system memory, and thereby allows for the controller to be used for applications in which throughput requirements and bus access constraints could otherwise conflict.

Abstract: A personal computer system unit has a planar card upon which is mounted a processor card. The processor has mounted thereon those components, except for system memory, which are most likely to be replaced for a system upgrade. The processor card has a printed circuit board with printed circuits thereon that terminate along one edge at contacts. Two aligned edge connectors are mounted on the planar board. One connector has a key which engages a slot on the edge of the processor card to align the many contacts with contact arms. Two levers are mounted on the card and cooperate with frame elements to insert, extract and latch the processor card. Each element also has a guide to align the processor card for insertion into the edge connectors.

Abstract: The functions of two virtual operating systems (e.g., S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices.

Abstract: The present off/on delay circuit operates within the power supply of a microcomputer system to interrupt transfer of regulated DC voltage to the system microcomputer and attachments in respect to indications of power disturbance and system switch status produced in the supply. Upon termination of such indications, this circuit selectively delays reappearance of regulated DC voltage to the level required for system operation so that whenever the microcomputer resets, the attachments must also reset; thereby preventing lockout impasses in the system rebooting process. The circuit operates in response to a plurality of DC voltage indications in the power supply, including at least an indication distinguishing the state of AC source power as either good or bad, and an indication distinguishing the state of a manually operable system power switch as either on or off.

Abstract: An apparatus and method for decreasing the memory requirements of BIOS in a personal computer system includes storing a first portion of BIOS in memory and a second portion on a direct storage access device. The personal computer system comprises a system processor, a random access main memory, a read only memory, and at least one direct access storage device. The first portion of BIOS only includes routines for initializing the system and the direct access storage device to read in a master boot record into the system from the direct access storage device. The master boot record includes a data segment and an executable code segment. The first BIOS portion vectors the system processor to execute the executable code segment of the master boot record. The executable code segment loads in the remaining BIOS portion from the direct access storage device into random access memory superseding the first BIOS portion.

Abstract: A personal computer system according to the present invention comprises a system processor, a random access memory, a read only memory, and at least one direct access storage device. A direct access storage device controller coupled between the system processor and direct access storage device includes a protection mechanism for protecting a region of the storage device. The protected region of the storage device includes a master boot record, a BIOS image and a system reference diskette image. The BIOS image includes a section known as Power on Self Test (POST). POST is used to test and initialize a system. Upon detecting any configuration error, system utilities from the system reference diskette image, such as set configuration programs, diagnostic programs and utility programs can be automatically activated from the direct access storage device.