Abstract: Parametric test data is taken on a sampled set of a particular integrated circuit (IC) using both an Automatic Test Equipment (ATE) tester and a system test motherboard. The parametric test data comprises maximum operating frequency, maximum operating temperature and minimum operating power supply voltage. A maximum operating frequency is determined at a particular fixed operating temperature and power supply voltage. A maximum operating temperature is determined at a particular fixed operating frequency and power supply voltage. Finally, a minimum operating power supply voltage is determined at a particular fixed operating frequency and temperature. Multiple two parameter graphs are plotted and the slope or numerical derivative for each plot is calculated as conversion factors. During a normal production run for the particular IC performance limit data is taken on the ATE tester comprising the same three parameters of maximum operating frequency at a particular temperature and power supply voltage.

Abstract: A method and apparatus for “drilling down” through a tree-based hierarchy are provided. Node descriptors corresponding to the nodes in the tree-based hierarchy are contained in entries in a data structure. Each node has a descriptor included in a first field in at least one entry in the data structure. A second field of the corresponding entry contains a node descriptor of a descendant node of the node corresponding to the descriptor in the first field. In response to user input, a descendant tree for a selected node is displayed by recursively searching in the first field of each entry in the data structure. Similarly, an ascendant tree is displayed by recursively searching in the second field of each entry in the data structure.

Abstract: A method of hierarchical LDAP searching in an LDAP directory service having a relational database management system (DBMS) as a backing store. The method begins by parsing an LDAP filter-based query for elements and logical operators of the filter query. For each filter element, the method generates an SQL subquery according to a set of translation rules. For each SQL subquery, the method then generates a set of entry identifiers for the LDAP filter query. Then, the SQL subqueries are combined into a single SQL query according to a set of combination rules chosen corresponding to the logical operators of the LDAP filter query.

Abstract: The present invention provides a semiconductor device assembly comprising a semiconductor chip, a heat sink having internal and external portions, and a housing that encapsulates the semiconductor chip and the internal portion. The internal portion thermally couples to one surface of the semiconductor chip. The present invention also provides a process of fabricating a semiconductor device assembly. The process includes: providing a semiconductor chip; providing a heat sink having internal and external portions; mechanically attaching a face of the chip to the internal portion; and applying an encapsulating material around the semiconductor chip and the internal portions.

Abstract: An apparatus and method for mediating a sequence of transactions across a fabric in a data processing system are implemented. A fabric bridge orders a preceding transaction and a subsequent transaction according to a predetermined protocol. Using the protocol a determination is made whether the subsequent transaction may be allowed to bypass the previous transaction, must be allowed to bypass the previous transaction, or must not be allowed to bypass the preceding transaction. Transactions include load/store (L/S) to system memory, and direct memory access (DMA) to system memory transactions.

Abstract: A method and apparatus for limited reprogrammability of fuse options in a semiconductor device is disclosed. In one embodiment, option circuitry includes a plurality of programmable devices each actuable from a first state to a second state and an option circuitry, which is coupled to the plurality of programmable devices to receive a plurality of logic signals reflecting the respective states of the plurality of programmable devices. The option circuitry is responsive to the plurality of logic signals to assert a particular one of a plurality of distinct option signals. The particular option signal is determined based on the particular combination of respective states of the plurality of programmable devices. The semiconductor device is responsive to assertion of each of the plurality of distinct option signals to operate in a distinct one of at least two operational modes.

Abstract: In a load/store unit within a microprocessor, load and store instructions are executed out of order. The load and store instructions are assigned tags in a predetermined manner, and then assigned to load and store reorder queues for keeping track of the program order of the load and store instructions. When a load instruction is issued for execution, a determination is made whether the load instruction is attempting to load data to a memory location that is the same as a previously executed store instruction is waiting to complete. If so, then the data waiting to be stored within the cache by the store instruction is directly forwarded to the load instruction.

Abstract: A method of hierarchical LDAP searching in an LDAP directory service having a relational database management system (DBMS) as a backing store. The method begins in response to a search query to the relational database. Search results retrieved in response to the search query are cached, preferably in a pair of caches in the directory service. The first cache receives a set of identifiers indexed by a filter key of the search query. The search results, namely entries corresponding to the set of identifiers, are then stored in the second cache. In response to subsequent issuance of the search query, the cached search results are then used in lieu of accessing the relational database to increase search efficiency. To maintain the integrity of the cached information, routines are provided to invalidate the caches during given directory service operations.

Abstract: An apparatus and method for mediating a sequence of transactions across a fabric in a data processing system are implemented. A fabric bridge orders a preceding transaction and a subsequent transaction according to a predetermined protocol. Using the protocol a determination is made whether the subsequent transaction may be allowed to bypass the previous transaction, must be allowed to bypass the previous transaction, or must not be allowed to bypass the preceding transaction. Transactions include load/store (L/S) system memory and L/S to input/output (I/O) device, and direct memory access (DMA) to system memory and DMA peer-to-peer transactions.

Abstract: A typical domino logic circuit has a foot device, which is the n-type evaluate transistor coupled between the n-type logic circuitry receiving the data inputs and the ground potential. This AND function provides an opportunity to move full domino AND blocks fed by full domino books of any type to the clock input of the source book. This makes the source book act like a pseudo-clocked book with a reset that must propagate from the AND block moved to its clock input. If the AND block were on the critical path, a complete stage of logic can be removed.

Abstract: The present invention allows for the simultaneous transmission of two digital signals from one integrated circuit to another. The two digital signals are encoded utilizing a voltage divider circuit and are then transmitted by one transmission line to the second integrated circuit chip. The second integrated circuit chip decodes the first digital signal and then utilizes this decoded digital signal to further decode the second digital signal.

Abstract: An apparatus and method for determining power consumption in logic devices including mixed static and dynamic logic blocks is implemented. Input logical signals are tagged as having dynamical behavior or static behavior, and the power consumption of the logic block determined according to the behavior of the input signal. If an input signal has dynamic behavior, an output signal making a transition in response thereto will make two transitions per clock cycle, and the per cycle power consumption of the logic block is accordingly weighted. In another embodiment, a Boolean behavior signal is calculated for each block from clock phase tags and “one cycle per cycle” circuit level simulations. The per cycle power consumption of each logic block receives a weight in response to the Boolean behavior signal, according the behavior of the block characterized thereby.

Abstract: An apparatus and method for the hardware support of multicolor software cursors is provided. The data structures defining the software cursor are mapped into the buffer of a video device supporting a multicolor sprite. Each color region in the software cursor is identified via the data structures, and a corresponding data value loaded into the buffer in response thereto. The color of the pixels in each region is specified by loading a color data value representing the color, obtained from one of the data structures, into a register associated with the respective region.

Abstract: As a program is replaced by the operating system running within a microprocessor, only those entries associated with the replaced program and resident within effective-to-real address translation units will be replaced. Those entries within the effective-to-real address translation units associated with the operating system and shared libraries, and any other software units operating within the microprocessor will not be invalidated.

Abstract: The present invention is a system, method, and computer readable medium for representing program event trace information in a way which is very compact and efficient, and yet supports a wide variety of queries regarding system performance. The tracing and reduction of the present invention may be dynamic, in which case information is obtained and added to the trace representation in real-time. Alternately, the tracing and reduction may be static, in which case a trace text file or binary file is obtained from a trace buffer, and the reduction takes place using the trace file as input. The trace information, whether obtained statically or dynamically, is represented as a tree of events. The present invention may be used to present many types of trace information in a compact manner which supports performance queries.

Abstract: An apparatus for encoding/decoding an associative cache set use history, and method therefor, is implemented. A five-bit signal is used to fully encode a four-way cache. A least recently used (LRU) set is encoded using a first bit pair, and a second bit pair encodes a most recently used (MRU) set. The sets having intermediate usage are encoded by a remaining single bit. The single bit has a first predetermined value when the sets having intermediate usage have an in-order relationship in accordance with a predetermined ordering of the cache sets. The single bit has a second predetermined value when the sets having intermediate usage have an out-of-order relationship.

Abstract: A node failure recovery mechanism for use in a data replicating system in a distributed computer environment wherein a plurality of servers are configured about one or more central hubs in a hub and spoke arrangement. In each of a plurality of originating nodes, updates and associated origination sequence numbers are sent to the central hub. The hub sends updates and associated distribution sequence numbers to the plurality of originating nodes. The hub tracks acknowledgments sent by nodes for a destination sequence number acknowledged by all nodes. Upon failure of a node, a node failure recovery method may be used to enable a “buddy” node to help the failed node gain readmission to a distribution group.

Abstract: In a processor, store instructions are divided or cracked into store data and store address generation portions for separate and parallel execution within two execution units. The address generation portion of the store instruction is executed within the load store unit, while the store data portion of the instruction is executed in an execution unit other than the load store unit. If the store instruction is a fixed point execution unit, then the store data portion is executed within the fixed point unit. If the store instruction is a floating point store instruction, then the store data portion of the store instruction is executed within the floating point unit.

Abstract: Pipelining and parallel execution of multiple load instructions is performed within a load store unit. When a first load instruction incurs a cache miss and proceeds to retrieve the load data from the system memory hierarchy, a second load instruction addressing the same load data will be merged into the first load instruction so that the data returned from the system memory hierarchy is sent to register files associated with both the first and second load instructions. As a result, the second load instruction does not have to wait until the load data has been written and validated in the data cache.

Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.