Abstract: A system for reviewing files which permits comments to be inserted in files to be viewed with a hypertext browser. When the hypertext mark-up language employed is HTML, text files are converted to an HTML representation. An HTML file is represented by a linked list of objects. Comment insertion markers and comment display objects are inserted at predefined points in the HTML linked list representation. The linked list is stored as a binary file and has a comment file associated with it. Access to the HTML file by reviewers and authors causes the regeneration of the HTML document by a Common Gateway Interface which recreates the linked list representation of the document from the binary file and which then generates HTML code from the linked list. Comments may be entered by reviewers working in parallel on the HTML document. Comments are displayed as inserted at the next regeneration of the HTML document by the system.

Abstract: A radio communication device modulates a received audio signal with an intermediate frequency (IF) signal before mixing with the radio frequency (RF) waveform for transmission by an antenna. A voltage controlled oscillator is utilized, which is tuned to N times the desired IF frequency. This voltage controlled oscillator is frequency modulated with the inputted audio signal to a deviation N times the desired IF source deviation. The voltage controlled oscillator is locked in a phase locked loop with a system reference frequency so that the output frequency is N times the desired IF frequency. The output of the voltage controlled oscillator is supplied to a “divide-by-N” frequency prescaler for generating a signal at precisely the right IF frequency and deviation.

Abstract: A method and system for utilizing bits in a collection of illegal op codes in order to enable pre-decoded instructions to be stored in an instruction cache without increasing the number of bits required to represent the pre-decoded instructions. Upon fetching an instruction from memory, the op code is examined for membership in a collection of illegal op codes. If the instruction op code is a member of this collection, the instruction may be re-encoded to use a different, common illegal op code. If the instruction op code is not a member of the collection of illegal op codes, but is instead an instruction to be stored in the instruction cache in a pre-decoded format, the additional pre-decoded information may be stored in the instruction encoding by utilizing the portion of the op code space which has been vacated by the re-encoding of the illegal op codes.

Abstract: A method and system for performing variable-sized memory coherency transactions. A bus interface unit coupled between a slave and a master may be configured to receive a request (master request) comprising a plurality of coherency granules from the master. Each snooping unit in the system may be configured to snoop a different number of coherency granules in the master request at a time. Once the bus interface unit has received a collection of sets of indications from each snooping logic unit indicating that the associated collection of coherency granules in the master request have been snooped by each snooping unit and that the data at the addresses for the collection of coherency granules snooped has not been updated, the bus interface unit may allow the data at the addresses of those coherency granules not updated to be transferred between the requesting master and the slave.

Abstract: The present invention discloses a lock indicator circuit used to indicate a phase lock condition between logic signals. The lock indicator circuit uses a phase detector that generates a pulse width proportional to the phase difference between a reference signal and a feedback signal. Another circuit generates, on each positive edge of the reference and the feedback signals, pulses whose widths are primarily dependent on fixed delay elements. These fixed pulse determine a window in which the pulse from the phase detector will fall as the two signals approach phase lock. Phase lock is signaled by the logic AND of the window pulse and the phase detector pulse. Other circuitry generates a phase lock indication signal if the phase lock signal remains true for a number of consecutive transitions of the reference signal. Likewise a phase unlock indication signal is generated if after phase lock indication, phase unlock occurs and remains for a number of consecutive transitions of the reference signal.

Abstract: Clock generation circuitry 1300 includes an oscillator 1302 for generating a first signal from a crystal 1301 of a selected oscillating frequency. A first frequency multiplier 1304 selectively multiplies the frequency of the first signal by a predetermined factor to obtain a second signal having a frequency of a preselected multiple of a first set of clock signals. A divider 1305 selectively divides the frequency of the second signal by a second factor to obtain a third signal of a selected frequency.

Abstract: The present application discloses a method and system of sharing reserved bandwidth among several connections issuing from a same physical port in an origin node of a packet switching communication network comprising a plurality of nodes interconnected with transmission links. At each request for establishing a connection i from an origin node to a destination node, the dependent connection management process: selects for connection i a routing path comprising one or a plurality of links from the origin node to the destination node: identifies on the selected path all consecutive links starting from the origin node and shared with another connection issuing from the same physical port; reserves on each link of these identified consecutive links an aggregate bandwidth for all connections issuing from the same physical port, said aggregate bandwidth being less than the sum of the bandwidth reserved for each connection considered individually.

Abstract: A WCDMA system includes a Base Station (BS) or forward transmitter and a pilot channel that transmits control signals between a Mobile Station (MS) and BS to reconfigure their transmitter/receiver according to the prediction of the channel power and channel power probability density function separated into three distinct equal probable regions. Data signals are encoded using a one-half Viterbi encoder and interleaved. The interleaved data bits are modulated using Quadrature Phase Shift Keying (QPSK) modulation. The QPSK data is multiplexed with the pilot channel and spread by an appropriate code in an OFDM transmitter modified by a long code. Output of the transmitter may be provided to two diverse antennas for reliable communications to the receiver. Data may be received at two diverse antennas. The outputs are provided to match filters coupled to a coherent rake receiver and a channel prediction system.

Abstract: A switched capacitor circuit 300, including a sampling capacitor 303, switches 301, 304 for charging the sampling capacitor 303 during a charging phase, and switches 302, 305 for transferring charge from the sampling capacitor 303 to a load 313 in the feedback loop of an operational amplifier 312 during a dump phase. Circuitry 701 controls the discharge of sampling capacitor 303 during the dump phase to minimize transients at the input of the operational amplifier 312 and thereby minimize input threshold voltage variation.

Abstract: In pause time based flow control systems having station-level granularity, a station or switch may detect congestion or incipient congestion and send a flow control frame to an upstream station, commanding that upstream station to temporarily stop (pause) sending data for a period of time specified in the flow control frame. The traffic pause gives the downstream station time to empty its buffers of at least some of the excess traffic it has been receiving. Since each downstream station operates independently in generating flow control frames, it is possible for the same upstream station to receive multiple, overlapping pause commands. If an upstream station which is already paused receives subsequent flow control frames from the same downstream station that triggered the pause, the upstream station's pause timer is rewritten using the pause times in the successive flow control frames.

Abstract: A system normally converts a parallel data word to a single serial data stream to use a high speed serial link. The parallel data word is partitioned into N sub-sets or nibbles and each nibble is then serialized and transmitted over N serial links using high speed differential drivers. Each of the N serialized nibbles are received in a differential receiver. The serialized nibbles are then coverted back into N parallel nibbles and the N parallel nibbles are then assembled back to the original parallel data word. To increase reliability, the received data is coupled to a tapped delay element having M stages of delay. A training sequence and algorithm are used to determine which of the taps of the delay element are a desired delay distance away from data transitions. These taps are then used to sample the incoming signals to reconstruct the parallel data word.

Abstract: A flow control process for a switching system having at least one switch core connected through serial communication links to remote and distributed Protocol Adapters or Protocol Engines through Switch Core Access Layer (SCAL) elements. For each input port i, the SCAL element contains a receive Protocol Interface corresponding to the adapter assigned to the input port i and a first serializer for providing attachment to the switch core by means of a first serial communication link. When the cells are received in the switch core, they are deserialized by means of a first deserializer. At each output port, the cells are serialized again by means of a second serializer and then transmitted via a second serial communication link, to the appropriate SCAL. The SCAL contains a second deserializer and a transmit Protocol Interface circuit for permitting attachment of the Protocol Adapter.

Abstract: A high performance integrated circuit (IC) with independent read and write data busses enables full simultaneous read and write data transfers between devices coupled to the buses. Multiple master and multiple slave devices communicate using the resources of a bus controller and a bus arbiter. Having separate read and write data busses with separate and independent arbitration allows reads and writes from different devices to occur simultaneously. Many high performance IC, like systems on a chip (SOC), have many different functional units communicating with a central processing unit (CPU). Many such CPUs have architectures that may cause in certain applications an unbalance between read and write traffic on the independent busses. Master and slave devices contain auxiliary internal read and write data buses multiplexed such that read or write data may be interchanged.

Abstract: A method and apparatus for performing a block-write to a memory device comprising at least one register, a data input port, at least one memory bank, and a hardware device to block-write data from the register to the memory device, including receiving a first portion of block-write data from a data bus during a first half of a clock cycle; then, producing a second portion of the block-write data, and block-writing the first and second portions of the block-write data from a write logic unit to the memory bank at a double data rate as determined by the clock cycle.

Abstract: The invention is a method for constructing an integrated circuit structure and an apparatus produced by the method. The method generally comprises constructing an integrated circuit structure by disposing a layer of doped oxide, the dopant being iso-electronic to silicon, and then reflowing the layer of doped oxide. Thus, the apparatus of the invention is an integrated circuit structure comprising a reflowed layer of doped oxide wherein the dopant is iso-electronic to silicon. In one particular embodiment, the method generally comprises constructing an integrated circuit feature on a substrate; disposing a layer of doped oxide, the dopant being iso-electronic to silicon, over the integrated circuit feature and the substrate in a substantially conformal manner; reflowing the layer of doped oxide; and etching the insulating layer and the oxide.

Abstract: When multi-destination traffic is distributed through a host or switch, the decision to distribute each frame is performed by each egress port and not the ingress port. Within a link aggregation group, the multi-destination frame is sent to each of the egress ports within the link aggregation group. Each of such ports will then determine whether it should re-transmit the frame. If not, the frame is discarded.

Abstract: A reduced dispersion optical waveguide and methods of fabricating the same are implemented. The optical waveguide may be fabricated in commercially practicable units without having to predetermine its length in a particular application. The reduced dispersion optical waveguide prevents optical pulse overlap in optical waveguide transmission systems operating over long distances or at high data rates.

Abstract: An integrated character recognition system for providing high-accuracy detection of a magnetic ink character string of a printed medium. The character recognition system includes a magnetic ink character recognition system for reading and decoding the magnetic ink character string. An optical character recognition system is also included performing the integrated character recognition system thereby overcoming many of the limitations presented by conventional technologies. A system and method for performing complete processing of a printed media having a magnetic ink character string utilizes both the optical and magnetic ink character recognition systems to perform virtually error-free character recognition of the magnetic ink character string.

Abstract: An apparatus for integer exception register (XER) renaming and methods of using the same are implemented. In a central processing unit (CPU) having a pipelined architecture, integer instructions that use or update the XER may be executed out-of-order using the XER renaming mechanism. Any instruction that updates the XER has an associated instruction identifier (IID) stored in a register. Subsequent instructions that use data in the XER use the stored IID to determine when the XER data has been updated by the execution of the instruction corresponding to the stored IID. As each instruction that updates XER data is executed, the data is stored in an XER rename buffer. Instructions using XER data then obtain the updated, valid, XER data from the rename buffer. In this way, these instructions can obtain valid XER data prior to completion of the preceding instructions. The XER data is retrieved from the XER rename buffer by indexing into the buffer by using an index derived from the stored IID.

Abstract: There is disclosed an apparatus for machining large diameter, thin-walled steel rings to precise tolerances. A ring of metal stock is placed within the jaws of a group of screw-type clamps located on a flat lathe faceplate. The clamps are evenly spaced around the ring of metal stock and each contains one or more pairs of opposing screws. The clamp screws are slowly advanced until the screws gently touch the inner surface and outer surface of the metal stock ring. The opposing screws are then gradually tightened until the ring of metal stock is locked in place. The equal and opposite forces exerted by the opposing screws hold the metal stock rigidly in place without inducing mechanical stresses in the ring that would otherwise warp the ring while it was mounted on the lathe faceplate.