Abstract: A new controller transfers data directly between the register of an I/O port and an ALU register in an operation that takes only one phase of a two-phase clock cycle. A transfer between an ALU register and main memory is also performed in one phase, and the entire transfer can be accomplished in one clock cycle. A connection is also provided between the ALU registers and the flag register, and when the incoming byte is a status byte, the controller can transfer the byte to the flag register where it can control the next instruction execution.