Abstract: A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value. Under each body region a respective lightly doped region of the second conductivity type is provided having a second resistivity value higher than the first resistivity value.
Type:
Grant
Filed:
January 21, 1999
Date of Patent:
May 8, 2001
Assignee:
STMicroelectronics S.r.l.
Inventors:
Ferruccio Frisina, Giuseppe Ferla, Salvatore Rinaudo
Abstract: The present invention relates to a method for fabricating an integrated circuit including an NPN-type bipolar transistor, including the steps of defining a base-emitter location of the transistor with polysilicon spacers resting on a silicon nitride layer; overetching the silicon nitride under the spacers; filling the overetched layer with highly-doped N-type polysilicon; depositing an N-type doped polysilicon layer; and diffusing the doping contained in the third and fourth layers to form the emitter of the bipolar transistor.