Abstract: An improved FET device in which the hot carrier immunity and current driving capability are improved, and the subthreshold leakage current is minimized. The device has a gate electrode with vertical sidewalls, and a thin layer of SiO.sub.2 over the electrode. A first polysilicon spacer is provided on the vertical sidewalls, with a second overlying oxide spacer over the first spacer. The top portion of the SiO.sub.2 layer between the gate electrode and the polysilicon spacer is made conductive enough to keep the gate electrode and the polysilicon spacer at the same potential. Lightly doped source and drain regions are provided.

Abstract: An improved electrically programmable and erasable memory device having a plurality of addressable single transistor cells, each transistor having spaced source and drain regions, a floating gate and a control gate. The improvement is a new tunneling insulator layer structure between the floating gate and the control gate. The improved tunneling layer is a dual layer formed of a outer silicon oxide layer and an inner silicon oxynitride layer.

Abstract: A structure and method are provided for forming a plug contact and a metal line pattern in a semiconductor device. A contact hole is etched through a first dielectric layer. A second dielectric layer is formed overlying the first layer having first opening that defines a first metal layer and plug contact. A nucleation layer, such as Ti/TiN or Ti/TiW, is formed on the exposed surfaces of the contact hole and first opening. A planarizing layer is formed which fills the contact hole, and at least partially fills the first openings thereby masking portions of the nucleation layer. Unmasked portions of the nucleation layer are removed and then the planarizing layer is removed. A metal is selectively deposited on the remaining nucleation layer portions to fill the contact hole and substantially filling the first opening. The metal in the first opening forms a plug contact to the bottom surface and a metal line pattern. This process has the advantages of forming two metal levels--i.e.

Abstract: A process where a blanket metal layer and a blanket SiO.sub.2 layer are formed on the surface of a semiconductor substrate. A metallurgy pattern is formed in the metal and SiO.sub.2 layers, and a thin conformal SiO.sub.2 layer formed over the metallurgy pattern. A relatively thick non-conformal SOG layer of insulating material is formed over the Si).sub.2 layer, which is etched back. Subsequently a relatively thick CVD layer is deposited on the surface. The steps are repeated to form additional metallurgy levels.

Abstract: A multichip array package for IC devices with a master semiconductor device supporting and electrically interconnected with a stacked array of subordinate devices. The interconnection structure has a peripheral row of contact pads on the master device. The subordinate devices each have a peripheral row of contact pads that corresponds to the peripheral row on the master device. Openings are provided through the contact pads on the subordinate devices that are in registry. The holes are filled with metal which interconnects the subordinate devices with the master device.

Abstract: A process improvement for enabling the development of low cost transistor devices, particularly MOS FETs, in annealed polysilicon formed on an insulator; the improvement resulting from the use of silicon ribbons as substrates.