Abstract: A method, apparatus, and computer instructions for handling updates. A database is queried to determine an effect of the update on the data processing system in response to detecting an update for the data processing system. A configuration of the data processing system is used in querying the database. A health status of the data processing system is selectively modified using the response to form a modified health status in response to receiving a response from the database.

Abstract: A computer implemented method, apparatus, and computer usable program code for preventing operational shock to a hard disk drive of a mobile computer. An exemplary method includes, responsive to activation by a user of an activation device associated with the mobile computer, changing a state of the activation device. The exemplary method also includes, responsive to the change of state of the activation device, issuing a priority standby command to the hard disk drive.

Abstract: On demand tracking of applications is provided by a mechanism of the present invention. After a user selects one or more units of execution of interest, a marker is assigned to each target object. Upon invocation of an application, an event is sent to an event handler if at least one target object is executed. The event handler gathers a process identifier and initiates a debugging, tracing or logging of the process on a target system.

Abstract: A method and system for validating selected layers of an integrated circuit design. A rundeck is edited to include IC layers and device structures of interest that may require validation. In some embodiments the IC layer of interest may include only metal. A layout versus schematic (LVS) comparison is performed using the edited rundeck and an error report is generated.

Abstract: A method and apparatus in a data controller in a storage drive for retrieving, evaluating, and processing a context that describes a direct memory access (DMA) request. The data controller includes a buffer for storing data transferred in response to execution of a DMA transfer request, a host address pointer pointing to a current location in the buffer, and a retrieval channel device. The retrieval channel device is configured to: fetch a context that describes a DMA transfer requested by a host computer, determine whether a current capacity of the buffer for transferring data exceeds a threshold, generate an instruction to transfer a second amount of data to complete at least a portion of the requested DMA transfer if the current capacity does exceed the threshold, assert the instruction generated by the retrieval channel device, and adjust the host address pointer by the second amount of data.

Abstract: A deep n-well is formed beneath the area of a capacitor structure. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch of shallow trench isolation is patterned over the n-well. The shallow trench isolation reduces and confines the inductively and/or capacitively coupled surface currents to small areas that are then isolated from the rest of the chip.

Abstract: A universal interface circuit and an associated method are provided that can supply a computer logic circuit, such as the components mounted upon an adapter card, with first and second inputs having first and second predetermined voltage levels, respectively, based upon power drawn from both first and second supply voltages. The interface circuit typically includes a first power supply circuit for providing the first input having the first predetermined voltage level in response to the first supply voltage. Additionally, the interface surface includes a regulator for generating an output having the second predetermined voltage level in response to the first supply voltage. The interface circuit further includes a second power supply circuit for providing an output that also has the second predetermined voltage level, albeit in response to the second supply voltage.

Abstract: System, apparatus and method for controlling the movement of data in a data processing system. The apparatus receives commands from at least one protocol engine and generates contexts representing the commands. The contexts are a data structure representing information for programming data transfers pursuant to the commands. Instruction requests based on the contexts are issued to the at least one protocol engine and to at least one DMA to efficiently control the movement of data to/from the at least one protocol engine from/to a local memory. The functions within the system are partitioned in a way that allows functions to be scaled for better performance and/or to support different protocols.

Abstract: A hardware-controlled data protection scheme can be used on a device providing buffering between two different protocols, especially where at least one of the protocols does not use fixed length blocks. A fixed block size is arbitrarily imposed on the data in order to calculate a cyclical redundancy code (CRC) for the block. Block sizes are restricted to a value of 2n, e.g., 2, 4, 8, 16, etc. The device is able to time-share and to receive or send data on more than one port while sharing the CRC engine between the ports. Intermediate values of the CRC for a given port are temporarily saved in a CRC register file. As a block of data for a given port is completed, a final CRC value for the block is saved to a CRC random access memory (RAM) located on the device and the entry in the register file is cleared. When the data is then output from the device, the CRC for the block is recalculated and checked against the saved value to be sure that they match.

Abstract: Improved layouts of binary and ternary content addressable memory cells (BCAM and TCAM) are shown. A content addressable memory cell layout has a plurality of P+ diffusion areas and a plurality of N+ diffusion areas that do not enclose isolation regions and on which shallow trench isolation stress can exert minimal influence on the drive current of the memories. Further, all transistors in the content addressable memory cell layout are oriented in the same direction to avoid unintended variations in electrical performance. The CAM layouts are “process friendly” to accommodate requirements of advanced process technologies such as the 90 nm process.

Abstract: A test schedule estimator for performing fixes on released software. In a preferred embodiment, historic data from similar builds are used with other data to estimate a time required to perform testing and release based on the number of fixes implemented.

Abstract: The present invention is a method and system for translating method calls to version-specified method calls. An interface to an underlying object is provided. Applications communicating with the underlying object use the interface. The interface is separate from the underlying object. Version-specific underlying objects are generated. Each one of the version-specific underlying objects is a different version of the underlying object. A plurality of translation objects, one for each version-specific underlying object, are generated for communicating between the interface and each one of the version-specific underlying objects. A translation object is used for translating an interface method call invoked on the interface to a version-specific method call for the underlying object for each version of the underlying object. All translation objects are generated from a single proxy class and a single invocation handler class.

Abstract: A universal interface circuit and an associated method are provided that can supply a computer logic circuit, such as the components mounted upon an adapter card, with first and second inputs having first and second predetermined voltage levels, respectively, based upon power drawn from both first and second supply voltages. The interface circuit typically includes a first power supply circuit for providing the first input having the first predetermined voltage level in response to the first supply voltage. Additionally, the interface surface includes a regulator for generating an output having the second predetermined voltage level in response to the first supply voltage. The interface circuit further includes a second power supply circuit for providing an output that also has the second predetermined voltage level, albeit in response to the second supply voltage.

Abstract: An apparatus and method for filtering glitches in data signals are provided. The apparatus and method provide a programmable glitch filter that may be programmed to filter glitches of different depths. The apparatus and method further provide a glitch filter that is programmable and incorporates a synchronizer for synchronizing the filtered output from the glitch filter to a different clock domain than that of the clock input.

Abstract: A collaboration client's behavior is changed according to context while collaborating on an internet. An HTTP request from a customer-side browser is sent to a web server via an information terminal support server. The web server then sends context in response to the request to the customer-side web browser via the information terminal support server. The information terminal support server then checks the contents of the context, and when it is determined that there is agreement with a predetermined condition, a command is inserted into the context. Context without the command inserted is sent to the customer-side web browser, and context with the command inserted is sent to the agent-side web browser. A client program of the agent-side information terminal then reads the embedded command using an API possessed by a web browser and carries out processing in order to prohibit form submission and form alteration and conceal specific forms or fields in accordance with the contents of this command.

Abstract: A method and system for facilitating communication between computer subnets are provided. One embodiment of the present invention comprises presetting buffers in an internal subnet, wherein the buffers help route external commands to a plurality of devices within the internal subnet. When a command from an external subnet is received by the internal subnet, the command is translated and sent to the proper internal device, as determined by the buffers. The command is then performed by the proper internal device. In another embodiment of the present invention, translation mapping are established for the internal subnet. When a command is received from an external subnet, the destination address associated with the command is translated to the address of the appropriate internal device, and the command is then sent directly to the internal device, which performs the command. By using either the buffer or translation mappings, the internal subnet appears to be a single device to the external subnet.

Abstract: The present invention provides for a method and computer program product for handling timeout in a standard RPC connection. First, a client establishes a connection with a server with unique identification. After submitting an RPC request, the client system will periodically make secondary requests to the server to determine if the server is still actively processing the primary RPC request. If the secondary request is processed successfully and the server indicates that the primary request is still in progress, the client will continue to wait until either the primary request completes or enough time elapses to warrant another secondary request. The success of the secondary request hinges on finding a match of identification for the primary and secondary requests. If the secondary request fails, this failure is treated as a sign that there is either a network or a server problem, and the client is triggered into taking appropriate corrective action.

Abstract: A silent mirroring protocol is provided, which eliminates the arbitration/selection times associated with all nexuses after the first nexus. During the initial SCSI bus negotiation, the initiator determines the transfer mode capability of all targets. The initiator establishes a group identification. Participants of the group recognize the group and look for an individual identification within the group. The initiator performs arbitration/selection with attention to the leader of the group. The initiator uses a message out phase with a vendor command to select a participant for a data block transfer. Each participant snoops the bus and recognizes when it is the target. If the initiator has more data to mirror, the process is repeated. When the last data block is transferred, the initiator sends a message out to the last participant, which is interpreted by the target leader as a command to release the bus. Each participant reselects the nexus initiator and returns a status.

Abstract: The present invention provides a diffusion resistor that is formed in the substrate. A diffusion region is formed within the substrate that contains a first and second contact region. These contact regions extend downward from the surface of the substrate. A third contact is located within the diffusion region between the first and second contacts. This contact also extends downward from the surface of the substrate. These contacts are connected to metal layers. The first and second contacts form the two ends of the diffusion resistor. The third contact forms a Schottky diode such that application of a voltage to this contact forms a depletion region within the diffusion region. The depletion region changes in size depending on the voltage applied to the third contact to change the resistance of the depletion resistor.

Abstract: A method of silicon design reproducibility enhancement using priority assignments prior to performing a conventional optical proximity correction process on a device. The present invention seeks to improve the manufacturability of VLSI devices. The present invention inserts a priority assignment step prior to the conventional OPC correction process in order to assert better control over transistor parameters. The priority assignment step sorts the layout by degree of importance to the cell/device performance. Areas designated as critical are given higher priority values while areas designated as non-critical are given lower priority values. The present invention imposes more precise accuracy requirements to high priority value areas and less precise accuracy requirements to low priority value areas. As a result, the present invention imposes the tightest accuracy requirements to critical areas of device performance, rather than attempting to achieve overall accuracy during the OPC correction process.