Abstract: Apparatus and method for controlling an operation of a test pin of a per-pin semiconductor device test system [10]. The apparatus includes pattern storage memory [42] for storing and for outputting information related to a state of the test pin for individual ones of a plurality of consecutive test cycles, pattern processor [14] having an input coupled to the pattern storage memory for generating for each of the test cycles words comprised of M bits, and a test pin control memory [18] having an input coupled to the output of the pattern processor for decoding each of the words into 2.sup.M or less command words. Each of the decoded command words includes a plurality of control bits. Predetermined ones of the plurality of control bits are coupled to pin driver electronics [24,28] for specifying, for each of the test cycles, at least one characteristic of an electrical signal transmitted to the test pin.

Abstract: The present invention relates to a memory cell, and more particularly to a single-bit, dual-port cell, and a single-sided read circuit for use with one or more such cells. The cell may, in one embodiment, be used in a static random access memory (RAM) array, and may be implemented in BICMOS technology on an integrated circuit. The cell has a flip-flop storage unit comprising a CMOS circuit of cross-coupled inverters coupled to dual CMOS pass gates to provide isolation and data transfer. The storage unit is also coupled to a bipolar read line driver in a particular configuration to accomplish rapid bit line pull-up or pulldown for high speed read operation. Several alternative embodiments are disclosed.

Abstract: A compact complementary transistor switch (CTS) memory cell structure utilizing both vertical PNP and vertical NPN transistors in gallium arsenide technology is described. The base region of the vertical PNP transistor merges with the collector region of the vertical NPN transistor. The collector region of the vertical PNP transistor merges with the base region of the vertical NPN transistor. The emitter of the vertical PNP transistor is at the top, and the emitter of the vertical NPN transistor is at the bottom in relation to the emitter of the vertical PNP transistor. This structure leads to improvements in memory density, performance and wireability of a memory array comprising many such cells. A novel yet simple process for making such compact CTS memory cells is also disclosed.

Abstract: A planar process for fabricating an optoelectronic integrated circuit device is described. The process includes the in situ formation of laser diode mirror facets comprising the steps of providing a semi-insulating gallium arsenide substrate having thereon layers of n-doped gallium arsenide, n-doped aluminum gallium arsenide, and undoped gallium arsenide; patterning and etching the undoped gallium arsenide layer into a mandrel having substantially vertical walls; establishing insulator sidewalls on the vertical walls; removing the mandrel, thereby exposing the inner walls of the insulator sidewalls and leaving the insulator sidewalls self-standing; removing the aluminum gallium arsenide using the insulator sidewall as a mask; and forming a laser diode within the region between the insulator sidewalls and creating the mirror facets with the inner walls of the insulator sidewalls. Mirror facets formed in accordance with this process are substantially free of contaminants.

Abstract: A low cost process for fabricating solder column interconnectons for an electronic package is described. The process includes the step of filling an array of pin holes in a pin mold with a lead/tin solder, which array of pin holes is in substantial registration with the array of conductive pads on one side of a chip carrier; heating the lead/tin solder in the pin mold such that the solder becomes molten and coalesces with the array of conductive pads of the chip carrier, thereby forming an array of miniature pins bonded to the array of conductive pads of the chip carrier; joining circuit components to the other side of the chip carrier; and reflowing an eutectic lead/tin solder paste screened to the corresponding array of conductive pads of a circuit board to bond the free ends of the array of miniature pins of the carrier to the corresponding array of conductive pads, thereby forming the solder column connnections between the chip carrier and the circuit board.

Abstract: Disclosed is a self-aligned GaAs, lightly doped drain metal-semiconductor field effect transistor. In one embodiment, the device consists of a shallow n.sup.- active channel region formed on a GaAs substrate, a Schottky gate overlying the n.sup.- region and highly doped and deep n.sup.+ source and drain regions formed on either side of the gate. In the channel region between the gate edges and the source/drain are positioned n-type source/drain extensions which have an intermediate depth and doping concentration to minimize the device series resistance, suppress short channel effects and permit channel length reduction to submicron levels.In a second embodiment, p-type pockets are provided under the source/drain extensions to better control the device threshold voltage and further reduce the channel length.In terms of the method of fabrication of the first embodiment, starting with a GaAs substrate an n.sup.- semiconductor layer is formed in the device active region.

Abstract: Disclosed is a method of forming solder terminals for a pinless module, preferably for a pinless metallized ceramic module. The method is comprised of the following steps: forming a substrate having a pattern of conductors formed onto its top surface and preformed via-holes extending from the top to bottom surface; applying a droplet of flux at at least one of said preformed via-hole openings of the bottom surface of said substrate to fill said via-holes with flux by capillarity and form a glob of flux at the bottom openings; applying a solder preform, i.e.

Abstract: A self-contained method and structure for partitioning, testing and diagnosing a multi-chip packaging structure. The method comprises the steps of electronically inhibiting all chips in the multi-chip package except for the chip or chips under test, creating a signature of the chip or chips under test by generating and applying random patterns to the chip or chips under test (referred to as the unit under test) and comparing the signature obtained to a "good machine" simulation signature. The structure comprises means for accomplishing the above method steps. A preferred structure comprises an semiconductor substrate having redundant self test circuitry built in and chips having ECIPT circuitry mounted on the semiconductor substrate. Either all or a portion of the self test circuitry, including the required multiplexers, etc., may be incorporated into the semiconductor substrate. ECIPT circuitry may also be built into the substrate below each chip site.

Abstract: Engineering changes in the wiring between semiconductor device chips supported on the same substrate are made using minimum substrate real estate and without the use of engineering change pads or discrete wires by the use of easily modified chip interposers. The interposers are inserted between respective chips and the substrate. The interposers comprise conductive vias and multiple internal wiring planes which are selectively connected to the vias.

Abstract: An integrated (silicon based) packaging/wiring structure provides for VLSI chips 4 to be placed within openings of somewhat larger size in a semiconductor interconnection wafer (IW, 2) supported by a carrier 1. The interconnection wafer 2 includes multilevel (ML) wiring planes and incorporated circuit components integrated in a less demanding technology as compared to the VLSI chips 4. Silicon contact chips 5 with conductive surface layers 22, 23 placed over the chip/IW plane provide for the required interconnections by means of needle-like structures 24 inserted in corresponding via holes. The needles are better suited to withstand shear strain than are conventional C-4 (Controlled Collapse Chip Connection) joints. Consequently a much higher number of chip pads can be provided. Power supply is effected via rather large-dimensioned conductive planes, e.g.

Abstract: A technique and apparatus for augmenting a random access memory with a fast clear or reset mechanism are described. A dynamic RAM having a fast clear mechanism in accordance with the present invention includes means for coupling a digital signal onto all bit lines; and fast reset control means operative for energizing the coupling means for connecting the digital signal to all of the bit lines such that upon energizing of a selected word line, all the bits connected to the selected word line are reset to the state of the digital signal, whereby reset time of the random access memory is reduced. The present invention is especially beneficial for incorporation in a frame buffer of an all points addressable raster scan display, and in a page buffer of an all points addressable printer wherein there is a requirement for high update performance.

Abstract: A two-electrode nematic liquid crystal display (LCD) device with inherent storage effect is described. The described storage effect LCD device, which can properly operate without refresh circuitry, can be of either the homogeneous or twisted nematic type. In accordance with the invention, the liquid crystal material-to-substrate anisotropic surface anchoring force is set sufficiently weak by surface treatment techniques, to prevent the restoration of the device to its quiescent state once the device has been driven temporarily to its active state by a temporary increase in an applied electric field.

Abstract: A hermetic electro-optic display cell has an enclosure for a liquid electrolyte comprising a wall of a plastics material, a lower inorganic base and an upper window both of which are impervious to the electrolyte. Impervious gasket means seals at least the lower edges of the wall to the base when clamped together. To render the wall hermetic an inorganic coating is provided around the exterior faces and along the edges at least as far as the gasket means. Metal is the preferred coating except for transparent faces where silica may be employed.

Abstract: An effective wind/breath screen for a microphone is described. The wind/breath screen includes a rigid perforated structure for enclosing the microphone. The microphone being physically isolated from the rigid perforated structure by a surrounding pad of air therebetween. A porous layer is utilized to enclose the rigid perforated structure thereby creating a pad of dead air between the microphone and the porous layer, whereby the speech signal reaches the microphone without substantial attenuation, and the wind/breath noise is suppressed. The present wind screen for a microphone is optimized for, and is particularly effective for voice data entry applications.

Abstract: A liquid-filled electro-optic display cell employs an elastomeric diaphragm to seal a filling orifice in the cell side wall. The orifice is surrounded by a rim and the diaphragm is retained over the rim in such a way as to seal the orifice while remaining free to flex over central portions of the orifice. This retention may be effected by means of an annular washer and clamping pin. In this way, sealing is effected and thermal expansion accommodated. The cell is filled by turning it until the orifice is uppermost and filling it until a convex meniscus is formed above the rim to ensure that the diaphragm seals the orifice without introduction of bubbles.

Abstract: In a red-emitting phosphor which includes ZnSe as a host material, copper (Cu) as an activator and aluminum (Al) as a coactivator, the improvement comprising the inclusion of a small amount of cobalt (Co) to provide superlinear characteristics to said phosphor in combination with said Cu and Al. A preferred range of concentration of said Co is 10.sup.-6 -2.times.10.sup.-5 g atom/mol. A specific application of said red-emitting superlinear phosphor is as a phosphor screen for a current density sensitive, single gun color CRT, when mixed with a green-emitting sublinear phosphor.

Abstract: An image is displayed in an electrolytic display by the reversible deposition on electrodes having non-scattering surfaces of a deposit having light scattering properties. The deposit scatters incident light out of the specular direction and the image is formed from one only of the specular and non-specular components of the emergent light.

Abstract: The present invention provides a method for fabricating large grain semiconductor ribbons suitable for use in solar cells. A molten semiconductor material is discharged onto a rotating cylindrical surface which is rotating with linear velocity of not greater than 36 m/sec.

Abstract: A laser drilling control system utilizing photoacoustic feedback is described. The control system provides an accurate monitoring of the laser drilling of a multilayered printed circuit board thereby allowing uniform drilling through layers of different optical and photoacoustic properties by both analyzing the photoacoustic feedback signals received, and adjusting optimally the laser parameters such as pulse duration, wavelength, energy, pulse repetition rate, and the number of pulses, for each successive layer. The system also provides an end point detection which prevents underdrilling overheating, and overdrilling of underlying layers and associated damages. According to another aspect of this invention, the control system can be used as a sensitive misregistration detector for aligning the laser beam to a selected drill site for subsequent drilling at the selected drill site.

Abstract: A heat dissipating system for cooling circuit chips or modules is described. The disclosed system includes circuit chips or modules which are vertically mounted, a gas at an elevated pressure being contained within an encased module for providing an enhanced thermal coupling between the chips or modules contained therein, and the walls of the encased module, whereby heat removal from the chips or modules is increased. This enhanced thermal coupling is combined with a reduction in the temperature of the walls of the encased modules so as to reduce the thermal resistance between the surrounding gas and the chips or modules to be cooled, whereby heat removal from the circuit chips or modules is substantially increased.