Abstract: Methods of organizing medical data include hierarchically relating a single type of medical or research event to medical data generated from the single type of medical or research event in a computer database environment. Organizing the data in this way enables a researcher to access medical data collected as part of a medical procedure performed on a large number of patients, but at different times. For example, the medical data may be viewed in a more hierarchical fashion, thereby enabling the researcher to further investigate potential relationships between other factors.

Abstract: A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region of the system memory. Each of the plurality of processing units includes a processor core and a cache memory including a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory and a cache controller. The cache controller, responsive to a store request from the processor core to update a particular VBSR line, performs a non-blocking update of the cache array in each other of the plurality of processing units contemporaneously holding a copy of the particular VBSR line by transmitting a VBSR update command on the interconnect fabric.

Abstract: Disclosed are a method and a system for grouping processor instructions for execution by a processor, where the group of processor instructions includes at least two branch processor instructions. In one or more embodiments, an instruction buffer can decouple an instruction fetch operation from an instruction decode operation by storing fetched processor instructions in the instruction buffer until the fetched processor instructions are ready to be decoded. Group formation can involve removing processor instructions from the instruction buffer and routing the processor instruction to latches that convey the processor instructions to decoders. Processor instructions that are removed from instruction buffer in a single clock cycle can be called a group of processor instructions. In one or more embodiments, the first instruction in the group must be the oldest instruction in the instruction buffer and instructions must be removed from the instruction buffer ordered from oldest to youngest.

Abstract: A battery charging system is disclosed. The battery charging system includes a battery cell, a voltage measurement circuit and an overvoltage protection circuit. The voltage measurement circuit measures a cell voltage of the battery cell. The overvoltage protection circuit is configured to stop charging the battery cell when a reading voltage measured by the voltage measurement circuit reaches an overvoltage setting value. The battery charging system also includes a battery charger for charging the battery cell, and a control unit for supplying a control voltage to the battery charger to perform feedback control of an output voltage of the battery charger. The battery charger includes a voltage feedback input for receiving a feedback voltage and a setting value input for receiving a setting voltage. The control voltage is generated based on the reading voltage and the setting voltage.

Abstract: A quality management framework system and method for operating a quality plan in a product development organization having quality objectives. The system includes a plurality of computer implemented tools accessible by users for operating a plurality of quality processes. Data relative to the quality processes is collected and aggregated to generate quality reports. Reports are analysed and problems are detected through a defect prevention process. Quality actions are initiated in a feedback quality management action tracking process.

Abstract: A reusable framework is utilized for creating a software architecture in a Service Oriented Architecture (SOA). After a general framework is created, that general framework is divided into a governance domain and an architecture domain. The architecture domain is further divided into architecture sub-domains within the architecture domain. Activities that are required for the governance domain and each of the architecture sub-domains and identified and described in detail, and owners and progress status markers for these activities are identified. The detailed descriptors of the activities, identified owners and progress status markers are then mapped onto a client-specific System Development Life Cycle (SDLC) work product to create an SOA-based software architecture. Deployment timelines for the governance domain and the architecture domain are determined, and a project plan for deploying the SOA-based software architecture is created.

Abstract: A computer-implementable method and system for managing software code documentation is disclosed. The method receives computer software code and documentation selected by a user and inserts one or more association keys in the selected code and one or more association keys in the selected documentation. The association keys are used to identify a portion of computer software documentation that corresponds with the computer software code. When the user wants to see documentation for a section of code, or code that corresponds to a section of documentation, the user selects the relevant text. The method receives the selected text, retrieves the association keys inserted in the selected text, determines whether the selected text is code or documentation, searches for documentation or code with matching association keys and alters the display of the matching documentation or code.

Abstract: A method, system, and computer program product for optimizing database queries in a data processing system. A query optimization (QO) utility maximizes the query coverage of Materialized Query Tables (MQTs) in order to efficiently process various types of incoming queries to a database engine. In particular, the QO utility enables MQT technology for nullable foreign key columns in a number of table joins involving fact tables and dimension tables, in which the fact tables and dimension tables have column data which are not null. The QO utility also enables MQT query matching for a relational database engine for non-additive measures, and improves the performance of existing query-matching capabilities for a relational database engine for additive measures. The QO utility specifies a number of functionally dependent relationships between the columns of a table in order to enhance the query matching abilities of the database engine.

Abstract: A technique for operating a high performance computing cluster (HPC) having multiple nodes (each of which include multiple processors) includes periodically broadcasting information, related to processor utilization and network utilization at each of the multiple nodes, from each of the multiple nodes to remaining ones of the multiple nodes. Respective local job tables maintained in each of the multiple nodes are updated based on the broadcast information. One or more threads are then moved from one or more of the multiple processors to a different one of the multiple processors (based on the broadcast information in the respective local job tables).

Abstract: A method of managing an electric utility grid includes geographically grouping a set of customer electric usage meters to create a set of fine sensors on a power grid. Each usage meter in the grouped set is capable of being remotely monitored, and each usage meter is at a different location along the power line. If a power anomaly is detected at the subset of meters, then power to the electric utility grid is adjusted to correct the anomaly.

Abstract: A method, system, and computer program product for enabling the transmission of data from a mobile device to a target device via one or more carrier mobile devices, in a communication network. A proxy mobile carrier (PMC) utility facilitates transmission of data from the originating mobile device to a target device in a network which is inaccessible to the originating mobile device. The PMC utility employs a collection of enhanced transmission enabling components (ETECs) to enable the data transfer via one or more carrier mobile devices. The ETECs include a message creation component, a network zone identification component, a future forwarding zone prediction component, a message acceptor component, a storage component, an inter-node communication component, and a message delivery component. By initiating specific interactions between the ETECs, the PMC utility facilitates the transmission of data from the mobile device to the target device via carrier mobiles.

Abstract: According to at least one embodiment, a method of data processing in a multiprocessor data processing system includes a requesting processing unit initiating an interconnect operation including a memory access request that indicates an acceptability of a variable amount of data to service the interconnect request for data. In response to snooping the memory access request on an interconnect, a snooper selects an amount of data to supply to the requesting processing unit and transmits the selected amount of data to the requesting processing unit. The requesting processing unit receives the selected amount of data and utilizes at least some of the selected amount of data to service a processor request.

Abstract: A cache memory includes a cache array including a plurality of congruence classes each containing a plurality of cache lines, where each cache line belongs to one of multiple classes which include at least a first class and a second class. The cache memory also includes a cache directory of the cache array that indicates class membership. The cache memory further includes a cache controller that selects a victim cache line for eviction from a congruence class. If the congruence class contains a cache line belonging to the second class, the cache controller preferentially selects as the victim cache line a cache line of the congruence class belonging to the second class based upon access order. If the congruence class contains no cache line belonging to the second class, the cache controller selects as the victim cache line a cache line belonging to the first class based upon access order.

Abstract: A design structure for performing cacheline polling utilizing store and reserve and load when reservation lost instructions is disclosed. In one embodiment a method is provided which comprises storing a buffer flag busy indicator data value within a first cacheable memory location and setting a load/store operation reservation on said first cacheable memory location via a store and reserve instruction. In the described embodiment, a data value stored within the first cacheable memory location is accessed via a conditional load instruction in response to a determination that the load/store operation reservation on the first cacheable memory location has been reset. Conversely, execution of the conditional load instruction is stalled in response to a determination that the load/store operation reservation on the first cacheable memory location has not been reset.

Abstract: A processing unit for a data processing system includes a processor core having one or more execution units for processing instructions and a register file for storing data accessed in processing of the instructions. The processing unit also includes a multi-level cache hierarchy coupled to and supporting the processor core. The multi-level cache hierarchy includes at least one upper level of cache memory having a lower access latency and at least one lower level of cache memory having a higher access latency. The lower level of cache memory, responsive to receipt of a memory access request that hits only a partial cache line in the lower level cache memory, sources the partial cache line to the at least one upper level cache memory to service the memory access request. The at least one upper level cache memory services the memory access request without caching the partial cache line.

Abstract: According to a method of simulation processing, an instrumented simulation executable model of a design is built by compiling one or more hardware description language (HDL) files specifying one or more design entities within the design and one or more instrumentation entities and instantiating instances of the one or more instrumentation entities within instances of the one or more design entities. Operation of the design is then simulated utilizing the instrumented simulation executable model. Simulating operation includes each of multiple instantiations of the one or more instrumentation entities generating a respective external phase signal representing an occurrence of a particular phase of operation and instrumentation combining logic generating from external phase signals of the multiple instantiations of the one or more instrumentation entities an aggregate phase signal representing an occurrence of the particular phase.

Abstract: A method, system, and computer-readable medium with executable code for connecting an outgoing phone call to a user destination device based on the time the phone call is initiated. A user of a user destination device transmits a policy information packet containing contact numbers of a primary user destination device and all secondary user destination devices that the user may be reached at during specific times of the day to a call originating device. In response to the user of a call originating device initiating a request to connect a phone call to the user destination device, the call originating device autonomously selects the correct recipient user destination device by interpreting the policy information packet. The call originating device then connects the phone call to the primary user destination device or to a secondary user destination device depending on the current time of day.

Abstract: An apparatus and method (200) are disclosed for expanded coverage in a mesh network (100). A communication device (140) incorporating teachings of the present disclosure may include, for example, a controller (302) managing operation of a transceiver (320) in communication with the mesh and programmed to acquire (202) a network identification from a mesh node (120), transmit (204) the network identification and appear as another mesh node to clients, and forward traffic from wireless clients to the mesh node. The communication device can operate (206) as a node in the mesh using the network identification and operate (208) as an independent router using a separate wireless router identifier. In another embodiment, the controller can be programmed to detect a network identification of an access point within a coverage area of a communication device (120), transmit a join message, and transmit authenticating information and security associations. Additional embodiments are disclosed.

Abstract: A system and method are disclosed for user fraud protection and prevention of access to a distributed network communication system. A first set of identification data associated with a first network access are stored. A second set of identification data associated with a second network access are stored. The first and second sets of identification data comprise a first computing device identification and a second computing device identification, respectively. If one or more fraud indicators are determined in the two sets of identification data, then the first and/or second network access may be revoked. The fraud indicators may include, e.g., use of the same username with different computing device identifications, use of the same computing device identification at different geographical locations, violation of a threshold for computing device identifications, violation of a threshold for authentication failures, and violation of a threshold for rate of network propagation by a user account.

Abstract: A method of data processing in a cache memory includes caching a plurality of cache lines of data in a corresponding plurality of entries in a cache array, where each of the plurality of cache lines includes multiple data granules. For each of the plurality of cache entries, a plurality of line coherency state fields indicates an associated coherency state applicable to two or more data granules. For at least a particular cache line among the plurality of cache lines, a granule coherency state field indicates a coherency state for a particular granule of the multiple data granules in the particular cache line, where the coherency state field indicated by the granule coherency state field differs from that indicated for the particular cache line by its line coherency state field.