Abstract: A method for synthesizing relative timing (RT) constraints on an integrated circuit design is disclosed. Initially, multiple trace status tables are received, and each of the trace status tables contains a trace error identified by a formal verification engine that was utilized to perform a relative timing (RT) verification on an integrated circuit design. An error causing signal is then recognized for each of the trace errors. For each of error causing signals, two associating signals are identified, and the two associating signals are then utilized to locate a common point of convergence (POC). The POC is further utilized to locate a common point of divergence (POD), and an RT constraint can be generated based on the identified POC and POD. All the generated RT constraints are applied to constrain the integrated circuit design such that the integrated circuit design is able to pass RT verifications in the future without any timing violations.

Abstract: A replicated state machine includes multiple state machine replicas. In response to a request from a client, the state machine replicas can execute a service for the request in parallel. Each of the state machine replicas is provided with a request manager instance. The request manager instance includes a distributed consensus means and a selection means. The distributed consensus means commits a stimulus sequence of requests to be processed by each of the state machine replicas. The selection means selects requests to be committed to the stimulus sequence. The selection is based on an estimated service time of the request from the client. The estimated service time of the request from the client is based on a history of service times from the client provided by a feedback from the state machine replicas. As such, requests from multiple clients are serviced fairly.

Abstract: A technique for operating a high performance computing (HPC) cluster includes monitoring workloads of multiple processors included in the HPC cluster. The HPC cluster includes multiple nodes that each include two or more of the multiple processors. One or more threads assigned to one or more of the multiple processors are moved to a different one of the multiple processors based on the workloads of the multiple processors.

Abstract: Synchronized pseudo-random number outputs are produced at a transmitter and a receiver of a high-speed serial interconnection. At the transmitter, using logic XOR operations, each data word of parallel data is selectively scrambled with one of the pseudo-random numbers and transmitted via a high-speed serial interface. The receiver de-scrambles the received serial data stream and restores the parallel data.

Abstract: A method, computer program product, and data processing system for collecting metrics regarding completion stalls in an out-of-order superscalar processor with branch prediction is disclosed. A preferred embodiment of the present invention selectively samples particular instructions (or classes of instructions). Each selected instruction, as it passes through the processor datapath, is marked (tagged) for monitoring by a performance monitoring unit. The progress of marked instructions is monitored by the performance monitoring unit, and various stall counters are triggered by the progress of the marked instructions and the instruction groups they form a part of. The stall counters count cycles to give an indication of when certain delays associated with particular instructions occur and how serious the delays are.

Abstract: During manufacture of an electronic device, an aerogel coating is applied to a first side of an IC substrate of a first IC. A bonding procedure is initiated, during which IC interconnects are either placed on the coated side of the substrate or on the opposite side of the substrate. The first IC is connected on a carrier to a second IC with the coated side of the first IC facing the second IC to reduce heat transmission to the second IC during operation of the first IC. The aerogel coating reduces thermal stress to the circuit board and surrounding components, reduces the risk of overheating of critical circuit components, provides chemical and mechanical insulation from contamination during subsequent wafer handling operations, and provides a thermal isolator between IC regions of dissimilar power dissipation, which isolator facilitates efficient thermal extraction from localized hotspots.

Abstract: A method of making a ball glove includes molding a plastic material to form a single-piece front palm lining that has a palm lining portion and five front finger lining portions, forming a back lining that has five rear finger lining portions, stitching together the front palm lining and the back lining to form a glove lining that has five inner finger stalls, tailoring a front ply that has a palm cover portion and five front finger cover portions, molding a plastic material to form a single-piece back ply that has five rear finger cover portions, assembling the front ply and the back ply to form an outer shell, forming a web, and assembling the web, the outer shell, and the glove lining to form the ball glove.

Abstract: A method for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.

Abstract: In a cache coherent data processing system including at least first and second coherency domains, a memory block is stored in a system memory in association with a domain indicator indicating whether or not the memory block is cached, if at all, only within the first coherency domain. A master in the first coherency domain determines whether or not a scope of broadcast transmission of an operation should extend beyond the first coherency domain by reference to the domain indicator stored in the cache and then performs a broadcast of the operation within the cache coherent data processing system in accordance with the determination.

Abstract: A process for making a protective assembly for an article, such as a circuit, includes forming a flexible layer of the protective assembly over the circuit to be protected during circuit operation, wherein said protective assembly is non-adhesive to the circuit and wherein the flexible layer is conformed to the topography of the circuit and non-adhesive to the circuit.

Abstract: A system and method for utilizing data mining to generate a policy document or to revise theory within a policy document. A data base of unknown events is mined for application to the development of a system management policy document. The results of the data mining of the database of unknown events are automatically incorporated into a policy document, subject to user approval, to produce a new policy document or an updated version of an existing policy document.

Abstract: A technique for maintaining input/output (I/O) command ordering on a bus includes assigning a channel identifier to I/O commands of an I/O stream. In this case, the channel identifier indicates the I/O commands belong to the I/O stream. A command location indicator is assigned to each of the I/O commands. The command location indicator provides an indication of which one of the I/O commands is a start command in the I/O stream and which of the I/O commands are continue commands in the I/O stream. The I/O commands are issued in a desired completion order. When a first one of the I/O commands does not complete successfully, the I/O commands in the I/O stream are reissued on the bus starting at the first one of the I/O commands that did not complete successfully.

Abstract: A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.

Abstract: The illustrative embodiments provide a method, system and computer program product for automatically capturing metadata using a template model. The template model is assembled for automatically capturing metadata during one or more stages of the life cycle of an application. Included in the template model are a description and a source of the metadata during a particular stage of the application lifecycle. The template model further includes multiple fields for dynamically capturing metadata. The template model fields may include: a stage field, an item field, a type field, specific source field, indicative field, a source list field, an analyzer reference field, default value field, and default reason field. A unique label associated with the stage field, of the template model, is read to identify the current stage of the lifecycle. The metadata associated with the current stage is automatically captured, then communicated to the application.

Abstract: A method, system and computer program product for enabling automated analysis of an extracted eScript to identify one or more problems within a configuration and script. The eScript is extracted from a Siebel repository and received in a DAVID (Development Application Verification Information on Demand for Siebel application where the VB.NET application, called SiebelParser, is utilized to conduct the analysis of the eScript. Occurrences of issues within an eScript are detected by SiebelParser. Issues within the eScript may include one or more of: empty event handlers, explicit object release, setting field values utilizing hard coded values, unnecessarily activated fields, call to next record after a call to delete record, and functions containing unnecessary code. Results from the analysis are reported to one log file document. The results of SiebelParser's log file are later incorporated to a spreadsheet by DAVID, to provide a more readable output format.

Abstract: A method and system for providing access to a shared resource utilizing selective locking are disclosed. According to one embodiment, a method is provided comprising receiving a request to perform a resource access operation on a shared resource, invoking a first routine to perform the resource access operation, detecting a data processing system exception generated in response to invoking the first routine, and invoking a second routine to perform the resource access operation in response to such detecting. In the described embodiment, the first routine comprises a dereference instruction to dereference a pointer to memory associated with the shared resource, the second routine comprises a lock acquisition instruction to acquire a global lock associated with the shared resource prior to a performance of the resource access operation and a lock release instruction to release the global lock once resource access operation has been performed.

Abstract: A method, system, and computer program product for efficiently providing software product updates in a client's computer system. A Software Product Update (SPU) utility initiates the software update process by downloading a response file. The response file comprises scripted code and encoded data for an update of application system files. The SPU utility processes the response file with the aid of a script processing engine (SPE), which is saved, along with installation files, on the client's computer system during an initial software product installation. The SPU utility sets the installation properties within the installation file set to values which allow the SPE to access and run the scripted code. The embedded binary data is decoded with the aid of the running scripted code. The SPU utility completes the update of application system files and the installation properties file, with the aid of the decoded embedded data.

Abstract: A data processing system includes a first processing unit and a second processing unit coupled by an interconnect fabric. The first processing unit has a first processor core and associated first upper and first lower level caches, and the second processing unit has a second processor core and associated second upper and lower level caches. In response to a data request, a victim cache line is selected for castout from the first lower level cache. The first processing unit issues on the interconnect fabric a lateral castout (LCO) command that identifies the victim cache line to be castout from the first lower level cache and indicates that a lower level cache is an intended destination. In response to a coherence response indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache.

Abstract: A design structure for performing cacheline polling utilizing a store and reserve instruction are disclosed. In accordance with one embodiment of the present invention, a first process initially requests an action to be performed by a second process. A reservation is set at a cacheable memory location via a store operation. The first process reads the cacheable memory location via a load operation to determine whether or not the requested action has been completed by the second process. The load operation of the first process is stalled until the reservation on the cacheable memory location is lost. After the requested action has been completed, the reservation in the cacheable memory location is reset by the second process.