Abstract: Methods for fabricating a layer or layers for use in package substrates and die spacers are described. In one implementation the layer or layers are fabricated to include a plurality of ceramic wells lying within a plane and separated by metallic via with recesses within the ceramic wells being occupied by a dielectric filler material.
Type:
Grant
Filed:
March 28, 2008
Date of Patent:
May 29, 2012
Assignee:
Intel Corporation
Inventors:
Aleksandar Aleksov, Vladimir Noveski, Sujit Sharan, Shankar Ganapathysubramanian
Abstract: Systems for cooling the backside of a semiconductor die located in a die-down integrated circuit (IC) package are described. The IC package is attached to the topside of a printed circuit board (PCB) with the backside of the die residing below the topside surface of the PCB. A cooling plate is attached to the backside of the die and thermally connected to a heat sink located above the topside surface of the PCB via conduits that pass through openings in the PCB.