Patents Assigned to 1-VIA LTD
  • Patent number: 12174651
    Abstract: A capacitor-less linear Low Drop Out (LDO) Voltage Regulating (VR) system and method with enhanced Power Supply Rejection (PSR), line transient response, and load transient response is disclosed. The system includes a current-summing amplifier to refine input voltage and error signals from an error amplifier circuit, improving regulation accuracy. Further, the system includes a Dynamic Current Bleeder (DCB) circuit to manage current flow, optimizing efficiency. Furthermore, a strategically placed compensation capacitor ensures stable voltage delivery despite load or input changes. To further enhance performance, a boost and reduce amplifier circuit continuously monitors and adjusts current of the error amplifier circuit, minimizing output voltage variations. The system effectively manages applications demanding highly regulated and stable voltage supplies.
    Type: Grant
    Filed: May 9, 2024
    Date of Patent: December 24, 2024
    Assignee: 1-VIA LTD
    Inventor: Suhas Rattan