Patents Assigned to 1366 Technologies Inc.
  • Patent number: 10633765
    Abstract: A main crucible of molten semiconductor is replenished from a supply crucible maintained such that there are always two phases of solid and liquid semiconductor within the supply crucible. Heat added to melt the solid material results in the solid material changing phase to liquid, but will not result in any significant elevation in temperature of the liquid within the supply crucible. The temperature excursions are advantageously small, being less than that which would cause problems with the formed product. The solid product material acts as a sort of temperature buffer, to maintain the supply liquid temperature automatically and passively at or very near to the phase transition temperature. For silicon, excursions are kept to less than 90° C., and even as small as 50° C. The methods also are useful with germanium. Prior art silicon methods that entirely melt the semiconductor experience excursions exceeding 100° C.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: April 28, 2020
    Assignee: 1366 TECHNOLOGIES, INC.
    Inventors: Ralf Jonczyk, Richard L Wallace, David S Harvey
  • Patent number: 10549476
    Abstract: A workpiece is transported using a porous belt, which belt delivers a workpiece to a chuck, upon which the workpiece is held by vacuum. The belt can be porous PTFE. A flexible stamp is preheated, before it is applied to a workpiece, by drawing the stamp toward a heated plate, for instance by vacuum.
    Type: Grant
    Filed: September 22, 2012
    Date of Patent: February 4, 2020
    Assignee: 1366 TECHNOLOGIES, INC.
    Inventors: Emanuel M. Sachs, Peter E. Kane, Holly G. Gates, Damian W. Harris, Benjamin F. Polito, Hector A. Inirio
  • Patent number: 10439095
    Abstract: A semiconductor wafer forms on a mold containing a dopant. The dopant dopes a melt region adjacent the mold. There, dopant concentration is higher than in the melt bulk. A wafer starts solidifying. Dopant diffuses poorly in solid semiconductor. After a wafer starts solidifying, dopant cannot enter the melt. Afterwards, the concentration of dopant in the melt adjacent the wafer surface is less than what was present where the wafer began to form. New wafer regions grow from a melt region whose dopant concentration lessens over time. This establishes a dopant gradient in the wafer, with higher concentration adjacent the mold. The gradient can be tailored. A gradient gives rise to a field that can function as a drift or back surface field. Solar collectors can have open grid conductors and better optical reflectors on the back surface, made possible by the intrinsic back surface field.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: October 8, 2019
    Assignee: 1366 TECHNOLOGIES, INC.
    Inventors: Ralf Jonczyk, Brian D. Kernan, G. D. Stephen Hudelson, Adam M. Lorenz, Emanuel M. Sachs
  • Patent number: 10072351
    Abstract: Semi-conductor wafers with thin and thicker regions at controlled locations may be for Photovoltaics. The interior may be less than 180 microns or thinner, to 50 microns, with a thicker portion, at 180-250 microns. Thin wafers have higher efficiency. A thicker perimeter provides handling strength. Thicker stripes, landings and islands are for metallization coupling. Wafers may be made directly from a melt upon a template with regions of different heat extraction propensity arranged to correspond to locations of relative thicknesses. Interstitial oxygen is less than 6×1017 atoms/cc, preferably less than 2×1017, total oxygen less than 8.75×1017 atoms/cc, preferably less than 5.25×1017. Thicker regions form adjacent template regions having relatively higher heat extraction propensity; thinner regions adjacent regions with lesser extraction propensity. Thicker template regions have higher extraction propensity. Functional materials upon the template also have differing extraction propensities.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: September 11, 2018
    Assignee: 1366 Technologies, Inc.
    Inventors: Emanuel M. Sachs, Ralf Jonczyk, Adam L. Lorenz, Richard L. Wallace, G. D. Stephen Hudelson
  • Publication number: 20180119309
    Abstract: A main crucible of molten semiconductor is replenished from a supply crucible maintained such that there are always two phases of solid and liquid semiconductor within the supply crucible. Heat added to melt the solid material results in the solid material changing phase to liquid, but will not result in any significant elevation in temperature of the liquid within the supply crucible. The temperature excursions are advantageously small, being less than that which would cause problems with the formed product. The solid product material acts as a sort of temperature buffer, to maintain the supply liquid temperature automatically and passively at or very near to the phase transition temperature. For silicon, excursions are kept to less than 90° C., and even as small as 50° C. The methods also are useful with germanium. Prior art silicon methods that entirely melt the semiconductor experience excursions exceeding 100° C.
    Type: Application
    Filed: April 28, 2016
    Publication date: May 3, 2018
    Applicant: 1366 TECHNOLOGIES, INC.
    Inventors: RALF JONCZYK, RICHARD L WALLACE, DAVID S HARVEY
  • Publication number: 20180019365
    Abstract: A semiconductor wafer forms on a mold containing a dopant. The dopant dopes a melt region adjacent the mold. There, dopant concentration is higher than in the melt bulk. A wafer starts solidifying. Dopant diffuses poorly in solid semiconductor. After a wafer starts solidifying, dopant can not enter the melt. Afterwards, the concentration of dopant in the melt adjacent the wafer surface is less than what was present where the wafer began to form. New wafer regions grow from a melt region whose dopant concentration lessens over time. This establishes a dopant gradient in the wafer, with higher concentration adjacent the mold. The gradient can be tailored. A gradient gives rise to a field that can function as a drift or back surface field. Solar collectors can have open grid conductors and better optical reflectors on the back surface, made possible by the intrinsic back surface field.
    Type: Application
    Filed: October 14, 2015
    Publication date: January 18, 2018
    Applicant: 1366 TECHNOLOGIES, INC.
    Inventors: RALF JONCZYK, KERNAN D BRIAN, G.D. STEPHEN HUDELSON, RICHARD L. WALLACE, ADAM M LORENZ
  • Patent number: 9815072
    Abstract: The present inventions relate to the formation of a thin polymer film on a substrate. Apparatus is described for transforming a solid polymer resist into an aerosol of small particles, electrostatically charging and depositing the particles onto a substrate, and flowing the particles into a continuous layer. Apparatus is further described for transforming solid resist into an aerosol of small particles by heating the resist to form a low viscosity liquid such as is compatible with nebulization and applying the techniques of jet or impact nebulization and aerosol particle sizing to form the aerosol. A method is further described of using ionized gas to confer charge onto the aerosol particles and using a progression of charging devices establish an electric field directing the flow of charged particles to the substrate. The progression of charging devices and associated apparatus results in high collection efficiency for the aerosol particles.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: November 14, 2017
    Assignee: 1366 Technologies Inc.
    Inventors: Guy M. Danner, Vladimir S. Tarasov, Peter E. Kane, Peter G. Madden, Holly G. Gates, Emanuel M. Sachs
  • Patent number: 9643342
    Abstract: A pressure differential can be applied across a mold sheet and a semiconductor (e.g. silicon) wafer (e.g. for solar cell) is formed thereon. Relaxation of the pressure differential can allow release of the wafer. The mold sheet may be cooler than the melt. Heat is extracted through the thickness of the forming wafer. The temperature of the solidifying body is substantially uniform across its width, resulting in low stresses and dislocation density and higher crystallographic quality. The mold sheet can allow flow of gas through it. The melt can be introduced to the sheet by: full area contact with the top of a melt; traversing a partial area contact of melt with the mold sheet, whether horizontal or vertical, or in between; and by dipping the mold into a melt. The grain size can be controlled by many means.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: May 9, 2017
    Assignee: 1366 Technologies, Inc.
    Inventors: Emanuel M. Sachs, Richard L. Wallace, Eerik T. Hantsoo, Adam M. Lorenz, G. D. Stephen Hudelson, Ralf Jonczyk
  • Publication number: 20170051429
    Abstract: Semi-conductor wafers with thin and thicker regions at controlled locations may be for Photovoltaics. The interior may be less than 180 microns or thinner, to 50 microns, with a thicker portion, at 180-250 microns. Thin wafers have higher efficiency. A thicker perimeter provides handling strength. Thicker stripes, landings and islands are for metallization coupling. Wafers may be made directly from a melt upon a template with regions of different heat extraction propensity arranged to correspond to locations of relative thicknesses. Interstitial oxygen is less than 6×1017 atoms/cc, preferably less than 2×1017, total oxygen less than 8.75×1017 atoms/cc, preferably less than 5.25×1017. Thicker regions form adjacent template regions having relatively higher heat extraction propensity; thinner regions adjacent regions with lesser extraction propensity. Thicker template regions have higher extraction propensity. Functional materials upon the template also have differing extraction propensities.
    Type: Application
    Filed: April 17, 2015
    Publication date: February 23, 2017
    Applicant: 1366 TECHNOLOGIES, INC.
    Inventors: EMANUEL M. SACHS, RALF JONCZYK, ADAM L. LORENZ, RICHARD L. WALLACE, G.D. STEPHEN HUDELSON
  • Patent number: 9425346
    Abstract: Patterned substrates for photovoltaic and other uses are made by pressing a flexible stamp upon a thin layer of resist material, which covers a substrate, such as a wafer. The resist changes phase or becomes flowable, flowing away from locations of impression, revealing the substrate, which is subjected to some shaping process. A typical substrate is silicon, and a typical resist is a wax. Workpiece textures include extended grooves, discrete, spaced apart pits, and combinations and intermediates thereof. Platen or rotary patterning apparatus may be used. Rough and irregular workpiece substrates may be accommodated by extended stamp elements. Resist may be applied first to the workpiece, the stamp, or substantially simultaneously, in discrete locations, or over the entire surface of either. The resist dewets the substrate completely where desired.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: August 23, 2016
    Assignees: 1366 Technologies Inc., MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Benjamin F. Polito, Holly G. Gates, Emanuel M. Sachs
  • Patent number: 9419167
    Abstract: An interposer sheet can be used for making semiconductor bodies, such as of silicon, such as for solar cell use. It is free-standing, very thin, flexible, porous and able to withstand the chemical and thermal environment of molten semiconductor without degradation. It is typically of a ceramic material, such as silica, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon carbonitride, silicon oxycarbonitride and others. It is provided between a forming surface of a mold sheet, and the molten material from which a semiconductor body will be formed. It may be secured to the forming surface or deposited upon the melt. The interposer sheet suppresses grain nucleation, and limits heat flow from the melt. It promotes separation of the semiconductor body from the forming surface. It can be fabricated before its use. Because free-standing and not adhered to the forming surface, problems of mismatch of CTE are minimized.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: August 16, 2016
    Assignee: 1366 Technologies, Inc.
    Inventors: Ralf Jonczyk, Emanuel M. Sachs
  • Publication number: 20150340540
    Abstract: Patterned substrates for photovoltaic and other uses are made by pressing a flexible stamp upon a thin layer of resist material, which covers a substrate, such as a wafer. The resist changes phase or becomes flowable, flowing away from locations of impression, revealing the substrate, which is subjected to some shaping process. A typical substrate is silicon, and a typical resist is a wax. Workpiece textures include extended grooves, discrete, spaced apart pits, and combinations and intermediates thereof. Platen or rotary patterning apparatus may be used. Rough and irregular workpiece substrates may be accommodated by extended stamp elements. Resist may be applied first to the workpiece, the stamp, or substantially simultaneously, in discrete locations, or over the entire surface of either. The resist dewets the substrate completely where desired.
    Type: Application
    Filed: January 16, 2014
    Publication date: November 26, 2015
    Applicants: MASSACHUSETTS INSTITUTE OF TECHNOLOGY, 1366 TECHNOLOGIES, INC.
    Inventors: Benjamin F. Polito, Holly G. Gates, Emanuel M. Sachs
  • Publication number: 20150037923
    Abstract: Processes increase light absorption into silicon wafers by selectively changing the reflective properties of the bottom portions of light trapping cavity features. Modification of light trapping features includes: deepening the bottom portion, increasing the curvature of the bottom portion, and roughening the bottom portion, all accomplished through etching. Modification may also be by the selective addition of material at the bottom of cavity features. Different types of features in the same wafers may be treated differently. Some may receive a treatment that improves light trapping while another is deliberately excluded from such treatment. Some may be deepened, some roughened, some both. No alignment is needed to achieve this selectively. The masking step achieves self-alignment to previously created light trapping features due to softening and deformation in place.
    Type: Application
    Filed: January 6, 2013
    Publication date: February 5, 2015
    Applicant: 1366 TECHNOLOGIES, INC.
    Inventors: Vladimir S. Tarasov, Ali Ersen, ERIC Stern, Jason M. Criscione, Emanuel M. Sachs
  • Publication number: 20150037922
    Abstract: A method for imparting a pattern to a flowable resist material on a substrate entails providing a resist layer so thin that during a stamp wedging process, the resist never completely fills the space between the substrate and the bottom surface of a stamp between wedge protrusions, leaving gap everywhere therebetween. A gap remains between the resist and the extended surface of the stamp. If the resist layer as deposited is somewhat thicker than the targeted amount, it will simply result in a smaller gap between resist and tool. The presence of a continuous gap assures that no pressure builds under the stamp. Thus, the force on the protrusions i determined only by the pressure above the stamp and is well controlled, resulting in well-controlled hole sizes. The gap prevents resist from being pumped entirely out of any one region, and thus prevents any regions from being uncovered of resist. The stamp can be pulsed in its contact with the substrate, repeatedly deforming the indenting protrusions.
    Type: Application
    Filed: September 22, 2012
    Publication date: February 5, 2015
    Applicant: 1366 TECHNOLOGIES, INC.
    Inventor: Emanuel M. Sachs
  • Publication number: 20140370643
    Abstract: Acid etch compositions for etching multicrystalline silicon substrates are disclosed which may include hydrofluoric acid, an oxidizer, an acid diluent, and soluble silicon. The soluble silicon may be hexafluorosilicic acid or ammonium fluorosilicate. Silicon substrates patterned with organic resist may be used with the acid etch compositions for selective silicon patterning for solar cell applications.
    Type: Application
    Filed: August 22, 2012
    Publication date: December 18, 2014
    Applicant: 1366 TECHNOLOGIES INC
    Inventors: Eric Stern, Bradley M. West, Jason Criscione
  • Publication number: 20140367887
    Abstract: A workpiece is transported using a porous belt, which belt delivers a workpiece to a chuck, upon which the workpiece is held by vacuum. The belt can be porous PTFE. A flexible stamp is preheated, before it is applied to a workpiece, by drawing the stamp toward a heated plate, for instance by vacuum.
    Type: Application
    Filed: September 22, 2012
    Publication date: December 18, 2014
    Applicant: 1366 TECHNOLOGIES, INC.
    Inventors: Emanuel M. Sachs, Peter E. Kane, Holly G. Gates, Damian W. Harris, Benjamin F. Polito, Hector A. Inirio
  • Publication number: 20140220171
    Abstract: A pressure differential can be applied across a mold sheet and a semiconductor (e.g. silicon) wafer (e.g. for solar cell) is formed thereon. Relaxation of the pressure differential can allow release of the wafer. The mold sheet may be cooler than the melt. Heat is extracted through the thickness of the forming wafer. The temperature of the solidifying body is substantially uniform across its width, resulting in low stresses and dislocation density and higher crystallographic quality. The mold sheet can allow flow of gas through it. The melt can be introduced to the sheet by: full area contact with the top of a melt; traversing a partial area contact of melt with the mold sheet, whether horizontal or vertical, or in between; and by dipping the mold into a melt. The grain size can be controlled by many means.
    Type: Application
    Filed: April 11, 2014
    Publication date: August 7, 2014
    Applicant: 1366 TECHNOLOGIES, INC.
    Inventors: Emanuel M. Sachs, Richard L. Wallace, Eerik T. Hantsoo, Adam M. Lorenz, G.D. Stephen Hudelson, Ralf Jonczyk
  • Publication number: 20140113156
    Abstract: An interposer sheet can be used for making semiconductor bodies, such as of silicon, such as for solar cell use. It is free-standing, very thin, flexible, porous and able to withstand the chemical and thermal environment of molten semiconductor without degradation. It is typically of a ceramic material, such as silica, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon carbonitride, silicon oxycarbonitride and others. It is provided between a forming surface of a mold sheet, and the molten material from which a semiconductor body will be formed. It may be secured to the forming surface or deposited upon the melt. The interposer sheet suppresses grain nucleation, and limits heat flow from the melt. It promotes separation of the semiconductor body from the forming surface. It can be fabricated before its use. Because free-standing and not adhered to the forming surface, problems of mismatch of CTE are minimized.
    Type: Application
    Filed: December 1, 2011
    Publication date: April 24, 2014
    Applicant: 1366 Technologies, Inc.
    Inventors: Ralf Jonczyk, Emanuel M. Sachs
  • Patent number: 8696810
    Abstract: A pressure differential is applied across a mold sheet and a semiconductor (e.g. silicon) wafer (e.g. for solar cell) is formed thereon. Relaxation of the pressure differential allows release of the wafer. The mold sheet may be cooler than the melt. Heat is extracted almost exclusively through the thickness of the forming wafer. The liquid and solid interface is substantially parallel to the mold sheet. The temperature of the solidifying body is substantially uniform across its width, resulting in low stresses and dislocation density and higher crystallographic quality. The mold sheet must allow flow of gas through it. The melt can be introduced to the sheet by: full area contact with the top of a melt; traversing a partial area contact of melt with the mold sheet, whether horizontal or vertical, or in between; and by dipping the mold into a melt. The grain size can be controlled by many means.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: April 15, 2014
    Assignee: 1366 Technologies, Inc.
    Inventors: Eerik T. Hantsoo, G. D. Stephen Hudelson, Ralf Jonczyk, Adam M. Lorenz, Emanuel M. Sachs, Richard L. Wallace
  • Patent number: 8669187
    Abstract: A porous lift off layer facilitates removal of films from surfaces, such as semiconductors. A layer, with porosities typically larger than the film thickness is provided where no film is desired. The film is applied over the porous layer and also where it is desired. The porous material and the film are then removed from areas where film is not intended. The porous layer can be provided as a slurry, dried to open porosities, or fugitive particles within a field, which disassociate upon the application of heat or solvent. The film can be removed by etchant that enters through porosities that have arisen due to the film not bridging the spaces between solid portions. Etchant attacks both film surfaces. Particles may have diameters of four to ten times the film thickness. Particles may be silica, alumina and ceramics. Porous layers can be used in depressions or on flat surfaces.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: March 11, 2014
    Assignee: 1366 Technologies, Inc.
    Inventors: Emanuel M. Sachs, Andrew M. Gabor