Abstract: A controller uses N dedicated ports to receive N signals from N non-volatile memories independent of each other, and uses a bus in a time shared manner to transfer data to and from the N non-volatile memories. The controller receives from a processor, multiple operations to perform data transfers, and stores the operations along with a valid bit set active by the processor. When a signal from a non-volatile memory is active indicating its readiness and when a corresponding operation has a valid bit active, the controller starts performance of the operation. When the readiness signal becomes inactive, the controller internally suspends the operation and starts performing another operation on another non-volatile memory whose readiness signal is active and for which an operation is valid. A suspended operation may be resumed any time after the corresponding readiness signal becomes active and on operation completion the valid bit is set inactive.