Abstract: A method and stacked semiconductor device having a top surface, a bottom surface, and at least one side surface that connects the top surface with the bottom surface. The bottom surface is formed of a substrate layer or a rear side contact layer arranged below the substrate layer. On the substrate layer, a first semiconductor layer of a first conductivity type is arranged and on the first semiconductor layer at least one second semiconductor layer of a second conductivity type is arranged. The first and second semiconductor layers are formed of a III-V material or consist of a III-V material. The first and second conductivity types are different. The top surface is at least partially formed by a passivation layer. Along the side surface, an amorphized and/or insulating region extending to a depth is formed, and the depth is perpendicular or substantially perpendicular to the layer stack.

Abstract: A stacked III-V semiconductor diode having an n+-layer with a dopant concentration of at least 1019 N/cm3, an n?-layer with a dopant concentration of 1012 -1016 N/cm3, a layer thickness of 10-300 microns, a p+-layer with a dopant concentration of 5×1018-5×1020 cm3, with a layer thickness greater than 2 microns, wherein said layers follow one another in the sequence mentioned, each comprising a GaAs compound. The n+-layer or the p+-layer is formed as the substrate and a lower side of the n?-layer is materially bonded with an upper side of the n+-layer, and a doped intermediate layer is arranged between the n?-layer and the p+-layer and materially bonded with an upper side and a lower side.

Abstract: A stacked III-V semiconductor component having a stack with a top, a bottom, a side surface, and a longitudinal axis. The stack has a p+ region, an n? layer, and an n+ region. The p+ region, the n? layer, and the n+ region follow one another in the specified order along the longitudinal axis and are monolithic in design, and include a GaAs compound. The n+ region or the p+ region is a substrate layer. The stack has, in the region of the side surface, a first and a second peripheral, shoulder-like edge. The first edge is composed of the substrate layer; the second edge is composed of the n? layer or of an intermediate layer adjacent to the n? layer and to the p+ region and the first and the second peripheral edges each have a width of at least 10 ?m.

Abstract: A stacked III-V semiconductor diode having an n? layer having a first surface, a second surface, a dopant concentration of 1012 N/cm3 to 1017 N/cm3 and a layer thickness of 50 ?m to 1,000 ?m, a p+ layer, which is integrally connected to the first surface and has a dopant concentration of 5·1018 N/cm3 to 5·1020 N/cm3, an n+ layer, which is integrally connected to the second surface and has a dopant concentration of at least 1019 N/cm3. The p+ layer, the n? layer and the n+ layer each having a monolithic design and each being made up of a GaAs compound. The dopant concentration of the n? layer having a first value on the first surface and a second value on the second surface, and the second value of the dopant concentration being greater than the first value at least by a factor between 1.5 and 2.5.

Abstract: A stacked III-V semiconductor diode having an n+-layer with a dopant concentration of at least 1019 N/cm3, an n?-layer with a dopant concentration of 1012-1016 N/cm3, a layer thickness of 10-300 microns, a p+-layer with a dopant concentration of 5×1018-5×1020 cm3, with a layer thickness greater than 2 microns, wherein said layers follow one another in the sequence mentioned, each comprising a GaAs compound. The n+-layer or the p+-layer is formed as the substrate and a lower side of the n?-layer is materially bonded with an upper side of the n+-layer, and a doped intermediate layer is arranged between the n?-layer and the p+-layer and materially bonded with an upper side and a lower side.

Abstract: A stacked III-V semiconductor component having a p+ region with a top side, a bottom side, and a dopant concentration of 5·1018-5·1020 N/cm3, a first n? layer with a top side and a bottom side, a dopant concentration of 1012-1017 N/cm3, and a layer thickness of 10-300 ?m, an n+ region with a top side, a bottom side, and a dopant concentration of at least 1018 N/cm3, wherein the p+ regions, the n? layer, and the n+ region follow one another in the stated order, are each formed monolithically, and each comprise a GaAs compound or consist of a GaAs compound, the n+ region or the p+ region is formed as the substrate layer, and the n? layer comprises chromium with a concentration of at least 1014 N/cm3 or at least 1015 N/cm3.

Abstract: A stacked III-V semiconductor diode that has an n+ layer having a dopant concentration of at least 1019 N/cm3, an n? layer having a dopant concentration of 1012 N/cm3 to 1016 N/cm3, a layer thickness of 10 ?m to 300 ?m, a p+ layer having a dopant concentration of 5·1018 N/cm3 to 5·1020 cm3 and a layer thickness greater than 2 ?m, the layers following each other in the specified order, each including a GaAs compound or being made from a GaAs compound and having a monolithic design, the n+ layer or the p+ layer being a substrate, and a lower side of the n? layer being integrally connected to an upper side of the n+ layer. The stacked III-V semiconductor diode including a first defect layer having a layer thickness greater than 0.5 ?m, the defect layer being situated within the n? layer.

Abstract: A stacked Schottky-diode having a stack with a top side and a bottom side. The stack has at least three semiconductor layers, and a first connection contact layer materially connected to the bottom side of the stack. A second connection contact layer is connected to the top side of the stack, wherein the second connection contact layer forms a Schottky contact. The second connection contact layer is disposed in a partial region of the top side and the second connection contact layer is bounded by edges. The first semiconductor layer, formed as an n+ layer, is placed on the bottom side of the stack and the first semiconductor layer. A second semiconductor layer, formed as an n? layer, is placed on the first semiconductor layer. A third semiconductor layer formed as a p? layer is placed on the second semiconductor layer.

Abstract: A stacked III-V semiconductor diode having an n+ substrate with a dopant concentration of at least 1019 cm?3 and a layer thickness of 50-400 ?m, an n? layer with a dopant concentration of 1012-1016 cm?3 and a layer thickness of 10-300 ?m, a p+ layer with a dopant concentration of 5·1018-5·1020 cm?3, including a GaAs compound and with a layer thickness greater than 2 ?m, wherein the n+ substrate and the n? layer are integrally joined to one another. A doped intermediate layer with a layer thickness of 1-50 ?m and a dopant concentration of 1012-1017 cm?3 is arranged between the n? layer and the p+ layer, and the intermediate layer is integrally joined to the n? layer and to the p+ layer.

Abstract: A method for manufacturing a layer stack having a p+-substrate, a p?-layer, an n?-layer and a third layer. A first partial stack and a second partial stack is produced, and an upper side of the first partial stack is integrally bonded with an upper side of the second partial stack , and the first partial stack has at least the p+-substrate. The second partial stack has at least the n?-layer, and the p?-layer is produced by epitaxy or implantation on an upper side of the p+-substrate or by epitaxy on the n?-layer. The p?-layer forms the upper side of the first partial stack or the second partial stack. The third layer is produced prior to or after the wafer bonding, and the n?-layer is produced after the wafer bonding by abrading an n?-substrate or prior to the wafer bonding on an n+-substrate.

Abstract: A stacked III-V semiconductor diode having an n+-layer with a dopant concentration of at least 1019 N/cm3, an n?-layer with a dopant concentration of 1012-1016 N/cm3, a layer thickness of 10-300 microns, a p+-layer with a dopant concentration of 5×1018-5×1020 cm3, with a layer thickness greater than 2 microns, wherein said layers follow one another in the sequence mentioned, each comprising a GaAs compound. The n+-layer or the p+-layer is formed as the substrate and a lower side of the n?-layer is materially bonded with an upper side of the n+-layer, and a doped intermediate layer is arranged between the n?-layer and the p+-layer and materially bonded with an upper side and a lower side.

Abstract: A stacked III-V semiconductor diode that has an n+ layer having a dopant concentration of at least 1019 N/cm3, an n? layer having a dopant concentration of 1012 N/cm3 to 1016 N/cm3, a layer thickness of 10 ?m to 300 ?m, a p+ layer having a dopant concentration of 5·1018 N/cm3 to 5·1020 cm3 and a layer thickness greater than 2 ?m, the layers following each other in the specified order, each including a GaAs compound or being made from a GaAs compound and having a monolithic design, the n+ layer or the p+ layer being a substrate, and a lower side of the n? layer being integrally connected to an upper side of the n+ layer. The stacked III-V semiconductor diode including a first defect layer having a layer thickness greater than 0.5 ?m, the defect layer being situated within the n? layer.

Abstract: A stacked III-V semiconductor diode having a p+ substrate with a dopant concentration of 5*1018 to 5*1020 cm?3, a layer thickness of 50-500 ?m, and formed of a GaAs compound, an n?-layer with a dopant concentration of 1014-1016 cm?3, a layer thickness of 10-300 ?m, and formed of a GaAs compound, an n+ layer with a dopant concentration of at least 1019 cm?3, a layer thickness less than 2 ?m and formed of a GaAs compound, wherein the n? layer and the n+ layer are materially connected to one another, a doped intermediate layer with a layer thickness of 5-50 ?m and a dopant concentration of 1015-1017 cm?3 is placed between the p+ substrate and the n? layer, and the intermediate layer is materially connected to the p+ substrate and to the n? layer.

Abstract: IGBT semiconductor structure having a p+ substrate, an n? layer, at least one p region adjacent to the n? layer, and at least one n+ region adjacent to the p region, a dielectric layer and three terminal contacts. The p region forms a first p-n junction together with the n? layer, and the n+ region forms a second p-n junction together with the at least one p region. The dielectric layer covers the first p-n junction and the second p-n junction. The second terminal contact is implemented as a field plate on the dielectric layer and a doped intermediate layer with a layer thickness of 1 ?m-50 ?m and a dopant concentration of 1012-1017 cm?3 is arranged between the p+ substrate and the n? layer, wherein the intermediate layer is integrally joined to at least the p+ substrate.

Abstract: A method for manufacturing a layer stack having a p+-substrate, a p?-layer, an n?-layer and a third layer. A first partial stack and a second partial stack is produced, and an upper side of the first partial stack is integrally bonded with an upper side of the second partial stack , and the first partial stack has at least the p+-substrate. The second partial stack has at least the n?-layer, and the p?-layer is produced by epitaxy or implantation on an upper side of the p+-substrate or by epitaxy on the n? layer. The p?-layer forms the upper side of the first partial stack or the second partial stack. The third layer is produced prior to or after the wafer bonding, and the n?-layer is produced after the wafer bonding by abrading an n?-substrate or prior to the wafer bonding on an n+-substrate.

Abstract: A stacked III-V semiconductor diode having a p+ substrate with a dopant concentration of 5*1018 to 5*1020 cm?3, a layer thickness of 50-500 ?m, and formed of a GaAs compound, an n?-layer with a dopant concentration of 1014-1016 cm?3, a layer thickness of 10-300 ?m, and formed of a GaAs compound, an n+ layer with a dopant concentration of at least 1019 cm?3, a layer thickness less than 2 ?m and formed of a GaAs compound, wherein the n? layer and the n+ layer are materially connected to one another, a doped intermediate layer with a layer thickness of 5-50 ?m and a dopant concentration of 1015-1017 cm?3 is placed between the p+ substrate and the n? layer, and the intermediate layer is materially connected to the p+ substrate and to the n? layer.

Abstract: A stacked III-V semiconductor diode having an n+ substrate with a dopant concentration of at least 1019 cm?3 and a layer thickness of 50-400 ?m, an n? layer with a dopant concentration of 1012-1016 cm?3 and a layer thickness of 10-300 ?m, a p+ layer with a dopant concentration of 5·1018-5·1020 cm?3, including a GaAs compound and with a layer thickness greater than 2 ?m, wherein the n+ substrate and the n? layer are integrally joined to one another. A doped intermediate layer with a layer thickness of 1-50 ?m and a dopant concentration of 1012-1017 cm?3 is arranged between the n? layer and the p+ layer, and the intermediate layer is integrally joined to the n? layer and to the p+ layer.

Abstract: A stacked Schottky-diode having a stack with a top side and a bottom side. The stack has at least three semiconductor layers, and a first connection contact layer materially connected to the bottom side of the stack. A second connection contact layer is connected to the top side of the stack, wherein the second connection contact layer forms a Schottky contact. The second connection contact layer is disposed in a partial region of the top side and the second connection contact layer is bounded by edges. The first semiconductor layer, formed as an n+ layer, is placed on the bottom side of the stack and the first semiconductor layer. A second semiconductor layer, formed as an n? layer, is placed on the first semiconductor layer. A third semiconductor layer formed as a p? layer is placed on the second semiconductor layer.