Abstract: A system and method for rasterization an image on a display through approximation, wherein the image is decomposed into a plurality of convex polygons, each convex polygon being defined by a plurality of original edges and each original edge being defined by two vertices. The coordinates of original vertices of an original edge are truncated, and the truncated coordinates are used to generate modified coordinates that define a modified edge. A plurality of modified edges defines a potentially changing region. If a selected region of a display device intersects this potentially changing region defined by the modified edges, then the first selected region is refreshed on the display device.

Abstract: A graphics processing chip which includes parallel texturing pipelines, with task allocation units which can bypass inoperative ones of said pipelines. Chips which have some but not all pipelines operative can still have full functionality, although performance is reduced.

Abstract: A 3D graphics architecture in which interfaces to memory are combined with pipeline processing. The rendering units are not all connected in a straight-through pipeline relationship: instead the rendering pipeline is “broken,” so that the stream of fragments (e.g. triangles) being processed is parked in memory. This turns out to be surprisingly efficient as a way to separate rendering processes where the workload balance is different. Preferably a first write to memory is performed after transformation and lighting calculations and before double-pass Z-buffering, and a second write to memory is performed before texturing. If Z-buffering or texturing is not being used for a particular rendering task, one or both of the memory interfaces can be switched off for that task. This economizes on memory bandwidth while retaining full flexibility.

Abstract: A graphics memory architecture in which row addresses are permuted, in a basically tile-oriented storage architecture, so that fast parallel access is provided both by scanlines (for video operations) and also by tiles (for graphics operations).

Abstract: A tile-oriented graphics processing system in which an additional level of caching is provided locally, at the output of a patch-processing graphics computation block. This additional local storage buffers the current tile, so that repeated accesses to the same tile can avoid pipelining delays connected with access to the main cache. (Even an on-chip cache, in a large chip, can impose access delays which are significant in relation to the computation speeds involved.

Abstract: A specialized processing chip (e.g. a graphics accelerator) in which the host interface provides access to the diagnostic registers in most of the complex logic on the chip, except for the host interface itself. This advantageously permits the host CPU to obtain direct access to register contents in the specialized chip.

Abstract: A 3D graphics architecture in which interfaces to memory are combined with pipeline processing. The rendering units are not all connected in a straight-through pipeline relationship: instead the rendering pipeline is “broken,” so that the stream of fragments (e.g. triangles) being processed is parked in memory. This turns out to be surprisingly efficient as a way to separate rendering processes where the workload balance is different. Preferably a first write to memory is performed after transformation and lighting calculations and before double-pass Z-buffering, and a second write to memory is performed before texturing. If Z-buffering or texturing is not being used for a particular rendering task, one or both of the memory interfaces can be switched off for that task. This economizes on memory bandwidth while retaining full flexibility.

Abstract: A method and system for optimizing the performance of a graphics processor system is disclosed. The graphics processor system includes multiple CPUs. The system has at least one application thread or master thread, and in addition each CPU is assigned a slave thread. In a first aspect, the method and system comprises assigning each slave to a particular CPU and causing the master thread to move between the processors to cause each slave thread to execute its graphics pipeline. This minimizes data motion due to application inputs being transferred from CPU to CPU. The method and system further includes providing a summary of relevant changes to graphics state to each slave, thus guaranteeing correct state without requiring synchronization around state updates. Accordingly a system and method in accordance with the present invention minimizes data motion during input and also minimizes synchronization associated therewith in a graphics processor system.

Abstract: A PCI compliant device having an internal function and a secondary PCI port for a second PCI device having additional functions. The device adapts its internal function and memory and the functions and memory of the second PCI device such that the host system sees only a single multi-function device, which appears to have the combined memories and functions of the adapter and second PCI device. Preferably the adapter itself includes a graphics pre-processor, and is connected to one or more rendering processors on the second PCI port.