Patents Assigned to 3DIS Technologies
  • Patent number: 11133264
    Abstract: The invention relates to a method for producing an electronic system, comprising: a step of forming a plurality of interconnect paths obtained via metal deposition on the sacrificial member to form a lower redistribution layer defining a plurality of lower connection ports connected to a plurality of inner connection ports; a step of depositing at least one electronic component on the lower redistribution layer; and a step of forming a plurality of three-dimensional interconnect paths obtained via metal deposition in order to connect the connectors of the electronic component to the inner connection ports of the lower redistribution layer.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: September 28, 2021
    Assignee: 3DIS TECHNOLOGIES
    Inventor: Ayad Ghannam
  • Publication number: 20200185331
    Abstract: The invention relates to a method for producing an electronic system, comprising: a step of forming a plurality of interconnect paths obtained via metal deposition on the sacrificial member to form a lower redistribution layer defining a plurality of lower connection ports connected to a plurality of inner connection ports; a step of depositing at least one electronic component on the lower redistribution layer; and a step of forming a plurality of three-dimensional interconnect paths obtained via metal deposition in order to connect the connectors of the electronic component to the inner connection ports of the lower redistribution layer.
    Type: Application
    Filed: August 8, 2018
    Publication date: June 11, 2020
    Applicant: 3DIS TECHNOLOGIES
    Inventor: Ayad Ghannam
  • Patent number: 10438923
    Abstract: The invention relates to a method for integrating at least one interconnection for the manufacture of an integrated circuit, including a step of depositing at least one insulating body onto a substrate including a horizontal surface, said insulating body comprising a first wall extending from the horizontal surface of the substrate to a high point of said insulating body and a step of depositing a one-piece electrical structure which is made of an electrically conductive material and extends on the horizontal surface of the substrate and the first wall of the insulating body, the first wall being vertically angled by more than 10 ?m and having a rising slope extending from the horizontal surface of the substrate to the high point of said insulating body.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: October 8, 2019
    Assignee: 3DIS Technologies
    Inventor: Ayad Ghannam
  • Publication number: 20180254258
    Abstract: The invention relates to a method for integrating at least one interconnection for the manufacture of an integrated circuit, including a step of depositing at least one insulating body onto a substrate including a horizontal surface, said insulating body comprising a first wall extending from the horizontal surface of the substrate to a high point of said insulating body and a step of depositing a one-piece electrical structure which is made of an electrically conductive material and extends on the horizontal surface of the substrate and the first wall of the insulating body, the first wall being vertically angled by more than 10 ?m and having a rising slope extending from the horizontal surface of the substrate to the high point of said insulating body.
    Type: Application
    Filed: September 14, 2016
    Publication date: September 6, 2018
    Applicant: 3DIS Technologies
    Inventor: Ayad Ghannam