Abstract: A set of techniques for rapidly computing a half-plane membership test for successive patches of pixels. By using an inheritance relation to carry forward values already computed at patch boundaries, the computational load for each successive patch is minimized. In a sample embodiment, just one interior point and one new boundary point are computed for each new patch of 64 pixels. Each of the 64 pixels can be described by an offset from one of the 5 reference points (i.e. the one interior point, the one newly computed boundary point, and 3 previously computed boundary points). By exploiting shift and complement relations, only a small number of offsets need to be independently computed (only 10 in this example). Since membership is determined merely by the sign of the relevant half-plane functions being computed, a simple compare between the half-plane function at the reference point and the half-plane function for the relevant offset suffices to evaluate the function's sign for that particular pixel.

Abstract: A system and method for performing 3D graphics copying operations in such a manner as to produce both a smooth image and smooth edges. The alpha value of each pixel is used to mark the pixels which are and are not part of the image to be copied, and removes unwanted pixels from bilinear filtering operations. After filtering, the resultant alpha values along the edges of the object are used to eliminate unwanted pixels, and to blend the object into the background of the image, which reduces or eliminates the "blocky" edges.

Abstract: A computer system having a pixel processing unit with multiple subprocessors receives positional data defining graphical objects from the CPU and writes pixel data into the image memory, and a display driver produces an image which partially includes the rendered pixels. The pixel processor is used to access patches of multiple contiguous pixels at a time, and process them in parallel. The patches used are defined, within the overall geometry of the image, to have aligned corners. The unit is also connected to receive synchronization signals from the display driver, conditioned on whether the current line being accessed by the driver is within a specified range of lines in the image space.

Abstract: In a demand-paged virtual memory system, the pages are arranged in the virtual memory space in groups. In order to translate an address from the virtual address space to a physical memory address space, the virtual group address component is input to a contents addressable memory (767), which outputs a group code (767), and the group code and virtual page address component (768X,Y) are input to a RAM page table (750) which outputs the page address. When the physical memory capacity is substantially smaller than the virtual address space, the CAM provides a large saving in page table size. In the case where the data-elements provide a plural-dimensional representation, for example as in pixel data, the pages include data elements which are contiguous in each of the plural dimensions in order to reduce the amount of page-swapping between the physical memory and a paging memory. The data-elements in the physical memory are accessible in parallel as contiguous patches.

Abstract: A data processing and memory system for transferring data elements page-by-page between several memories and modifying the data elements in the first memory. In order to reduce the set-up time when generating a new image, the processor stores the background color of the image for each new page. Then, when each new page is transferred to one of the memories, the background color is repeated for each data-element in the page.

Abstract: A data array processing system comprises a memory system for storing an array of data elements and addressable by a single address, a plural number N of processors (PROC(0)-(15)) capable of processing data elements in parallel, and an address bus. In order to allow parallel access to the memory system where possible, but permit the processors also to access different addresses, each processor is selectable to supply its respective required address (xq, yq) via the address bus to the memory system to access the memory, and each non-selected processor is operable to determine whether it requires access to the address (xq, yq) on the bus, and if so to access the memory system at the same time as the selected processor.

Abstract: A system for storing and processing an array of data-elements formatted as a plurality of pages of the data elements, and especially for use in a demand-paged dual memory system, comprises a memory in which each memory location has a capacity of, for example, 32 bits and a processing means for processing data elements and reading the data elements from and/or writing them to the memory. In order to enable full use to be made of the memory and to facilitate the use of demand-paging when dealing with data-elements having less bits, for example 16 or 8 bits, a plurality of such data-elements are stored at different bit levels in each memory location so that at no memory location is there stored data-elements from more than one page.

Abstract: A multiprocessor system which includes a control processor and a high-level data-transfer processor. Both of these two processors are docked by a shared variable-duration clock. The duration of the clock is adjusted on the fly, to accommodate whichever of the two processors needs the longest cycle time on that particular cycle. Thus, the control processor 110 and the data transfer processor 120 are enabled to run synchronously, even though they are concurrently running separate streams of instructions.