Abstract: A system and method for improving error detection and correction for transmitted data. An iterative error detection method is used to determine a relative likelihood that decoded data is an accurate representation of the original data. An independent error correction unit operates on the decoded data and a result from the independent error correction unit is injected into the iterative error detection method to improve the reliability of the error detection method.

Abstract: A correlator circuit for calculating the correlation between a signal sequence and a binary reference sequence. A unique method of calculating the correlation value between the two sequences provides for the reduction in necessary computations and, as a result, a reduction in the amount of time expended in calculating the correlation is realized.

Abstract: A block interleaver is provided using a relatively small register file and a larger random access memory (RAM). In one embodiment, the size of the RAM is larger than the size of the register file by at least one order of magnitude. As a result, the register file consumes significantly less power than the RAM for similar operations. The register file receives a stream of sequential data values and stores the data values in a column order. The data values are then read from the register file in a row order. The data values read from the register file in a row order are then written to the RAM in a row order. The data values are then read from the RAM in a row order, thereby creating an interleaved data stream. In a particular embodiment, the data values are written to the RAM in a staggered row order and read from the RAM in a sequential row order. All accesses to the RAM are performed using the full width of the RAM, such that no unnecessary power is used to access the RAM.

Abstract: A system and method for improving error detection and correction for transmitted data. An iterative error detection method is used to determine a relative likelihood that decoded data is an accurate representation of the original data. An independent error correction unit operates on the decoded data and a result from the independent error correction unit is injected into the iterative error detection method to improve the reliability of the error detection method.

Abstract: A correlator circuit for calculating the correlation between a signal sequence and a binary reference sequence. A unique method of calculating the correlation value between the two sequences provides for the reduction in necessary computations and, as a result, a reduction in the amount of time expended in calculating the correlation is realized.

Abstract: A circuit for providing a function of a plurality of consecutive bits in a shift register is provided. The circuit includes a 2-input logic gate having a first input terminal connected to receive a bit being shifted into the shift register, and a second input terminal coupled to receive a bit being shifted out of the shift register. The circuit further includes a sequential logic device having an input terminal coupled to an output terminal of the 2-input logic gate, an output terminal that provides the function, and a control terminal coupled to receive a control signal for resetting the sequential logic device. In one embodiment, the 2-input logic gate is an exclusive OR gate, and the sequential logic device is a toggle flip-flop. In this embodiment, the function is a logical exclusive OR of the consecutive bits in the shift register. The function is implemented by initializing an output signal of the sequential logic device when the consecutive bits of the shift register have a predetermined value.