Abstract: Wafer scale integrated circuitry which uses a cluster of wafer components, each component having a plurality of processing elements and a network element connected thereto for controlling the transfer of information to and from the processing elements. The network element is connected to network elements of other wafer components of the cluster for controlling the transfer of information to and from such other network elements. One or more redundant groups of processing elements are formed on the wafer components of the cluster, each redundant group being configured so that the processing elements in the group reside on different ones of the wafer components.