Patents Assigned to 501 Fujitsu Limited
  • Patent number: 5082695
    Abstract: A method of fabricating an X-ray exposure mask including the steps of forming a .beta.-SiC membrane by chemcial vapor deposition and simultaneously doping the membrane with at least one of phosphorous, boron, nitrogen and oxygen.
    Type: Grant
    Filed: February 24, 1989
    Date of Patent: January 21, 1992
    Assignee: 501 Fujitsu Limited
    Inventors: Masao Yamada, Masafumi Nakaishi, Kenji Nakagawa, Yuji Furumura, Takashi Eshita, Fumitake Mieno
  • Patent number: 5024958
    Abstract: A high-speed compound semiconductor device includes semiconductor layers of a group III-V alloy laminated in a vertical direction. The device uses a base electrode that contacts side walls and covers a step portion of a base layer. The device includes an intermediate layer positioned between and comprising a different semiconductor material than that of base and collector layers. The intermediate layer has a different etching rate than those of the base and collector layers. The intermediate layer can be a collector-side barrier layer formed between the collector and base layers in a HET or RHET device. The device of the present invention has reduced capacitance between the base and collector layers and reduced base layer resistance.
    Type: Grant
    Filed: October 25, 1990
    Date of Patent: June 18, 1991
    Assignee: 501 Fujitsu Limited
    Inventor: Yuji Awano
  • Patent number: 4967252
    Abstract: A high-speed compound semiconductor device includes semiconductor layers of a group III-V alloy laminated in a vertical direction. The device uses a base electrode that contacts side walls and covers a step portion of a base layer. The device includes an intermediate layer positioned between and comprising a different semiconductor material than that of base and collector layers. The intermediate layer has a different etching rate than those of the base and collector layers. The intermediate layer can be a collector-side barrier layer formed between the collector and base layers in a HET or RHET device. The device of the present invention has reduced capacitance between the base and collector layers and reduced base layer resistance.
    Type: Grant
    Filed: March 15, 1989
    Date of Patent: October 30, 1990
    Assignee: 501 Fujitsu Limited
    Inventor: Yuji Awano