Abstract: A method of monitoring a conveyance apparatus within a conveyance system including: detecting, using a sensing apparatus, at a first conveyance apparatus location at least one of an acceleration of the conveyance apparatus, temperature data of the conveyance system, and pressure data proximate the conveyance apparatus; determining a health level of the conveyance system at the first conveyance apparatus location in response to at least one of the acceleration of the conveyance apparatus, the temperature data of the conveyance system, and the pressure data proximate the conveyance apparatus; and displaying the health level for the conveyance system at the first conveyance apparatus location on a display device.

Abstract: Variable sleeve clearance control systems for gas turbine engines are disclosed. An example variable sleeve clearance control system for a gas turbine engine includes a sleeve comprising a first end and a second end, the first end of the sleeve coupled to a first spring that biases the sleeve inward, and the second end of the sleeve coupled to a second spring that biases the sleeve outward, a proximity sensor to measure a clearance width, and a controller for each of the first and second springs, the controller to obtain the measured clearance width from the proximity sensor and determine a response of the first and second springs.

Abstract: Disclosed herein are systems and processes for removing heavies during the liquefaction of a natural gas. The processes include dissolving the heavies in the natural gas by adding external natural gas liquid (NGL), followed by a staged removal of the natural gas liquid (NGL) and dissolved heavies.

Abstract: The disclosed methods include: determining context data for a digital request data object based on a received first input; executing, based on the context data and the first input: a first and a second computing operation; generating a first digital record indicating: summary data for the first and second computing operations, and first state data associated with transitioning the digital request data object from a first data state to a second data state; updating context data based on the first digital record; executing, based on the updated context data and/or a received second input: a third and a fourth computing operation; generating a second digital record indicating: summary data for the third and the fourth computing operations, and second state data associated with transitioning the digital request data object from: the second data state to a third data state, and from the third data state to a fourth data state.

Abstract: A semiconductor device includes a first fin, a second fin, and a third fin protruding above a substrate, where the third fin is between the first fin and the second fin; a gate dielectric layer over the first fin, the second fin, and the third fin; a first work function layer over and contacting the gate dielectric layer, where the first work function layer extends along first sidewalls and a first upper surface of the first fin; a second work function layer over and contacting the gate dielectric layer, where the second work function layer extends along second sidewalls and a second upper surface of the second fin, where the first work function layer and the second work function layer comprise different materials; and a first gate electrode over the first fin, a second gate electrode over the second fin, and a third gate electrode over the third fin.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. A first interconnect conductive structure extends through the first interconnect dielectric layer. A first capping layer is arranged over the first interconnect conductive structure, and a second capping layer is arranged over the first capping layer. The first capping layer includes a first two-dimensional material that is different than a second two-dimensional material of the second capping layer. An etch stop layer is arranged over the first interconnect dielectric layer and the second capping layer. The integrated chip further includes a second interconnect dielectric layer arranged over the etch stop layer and a second interconnect conductive structure extending through the second interconnect dielectric layer and the etch stop layer to contact the first interconnect conductive structure.

Abstract: An electro-optically controlled active-matrix system comprises a system substrate, row wires extending in a row direction disposed on the system substrate, a row controller providing a row electrical signal to each row wire, column light-pipes extending in a column direction disposed on the system substrate, a column controller providing a column optical signal to each column light-pipe, and pixels disposed over the system substrate. Each pixel can comprise a pixel circuit that is uniquely responsive to a row wire and to a column light-pipe, the pixel circuit receiving the row electrical signal from the row wire and receiving the column optical signal from the column light-pipe. In some embodiments, column wires carrying column electrical signals extend in a column direction over the system substrate and the pixel circuit is capacitively coupled to the row wire, the column wire, or both.

Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.

Abstract: A plurality of devices for testing, connected in series using one or more redistribution layers (RDLs), are used to perform a semiconductor device test on a plurality of dies. As a result, the semiconductor device test may support thousands of gross dies per wafer or greater (e.g., 10,000 dies or greater). Furthermore, the RDL(s) may be removed after use. In some implementations, the devices for testing corresponding to the dies may execute the semiconductor device test sequentially. Accordingly, test data may be generated and may include a bit sequence, where a first bit in the bit sequence indicates an overall outcome for the test and one or more subsequent bits in the bit sequence indicate respective outcomes for each semiconductor dies or for each line of the semiconductor device test.

Abstract: This disclosure relates to a foamable resin composition containing a nitrogen gas-generating compound and methods of using the composition for loss circulation control.

Abstract: Aspects of the disclosure relate to using computer vision methods to forecast damage. A computing platform may receive historical images comprising aerial images of residential properties and historical loss data corresponding to the residential properties. Using the historical images and the historical loss data, the computing platform may train a computer vision model, which may configure the computer vision model to output loss prediction information directly from an image. The computing platform may receive a new image corresponding to a particular residential property, and may analyze the new image, using the computer vision model, which may directly result in a likelihood of damage score. Based on the likelihood of damage score, the computing platform may send likelihood of damage information and one or more commands directing a user device to display the likelihood of damage information, which may cause the user device to display the likelihood of damage information.

Abstract: A method of forming a semiconductor device includes applying an adhesive material in a first region of an upper surface of a substrate, where applying the adhesive material includes: applying a first adhesive material at first locations of the first region; and applying a second adhesive material at second locations of the first region, the second adhesive material having a different material composition from the first adhesive material. The method further includes attaching a ring to the upper surface of the substrate using the adhesive material applied on the upper surface of the substrate, where the adhesive material is between the ring and the substrate after the ring is attached.

Abstract: A memory device includes a bit line (BL); a source line (SL); and a plurality of non-volatile memory cells operatively coupled between the BL and SL, respectively. Each of the plurality of non-volatile memory cells includes a resistor with a variable resistance, a first transistor, and a second transistor that are coupled to each other in series. In response to a first one of the non-volatile memory cell not being read and a second one of the non-volatile memory cell being read, a voltage level at a first node connected between the first and second transistors of the first non-volatile memory cell is greater than zero.

Abstract: A method of making a chip includes depositing a first polysilicon layer on a top surface and a bottom surface of a substrate. The method further includes patterning the first polysilicon layer to define a recess, wherein the first polysilicon layer is completed removed from the recess. The method further includes implanting dopants into the substrate to define an implant region. The method further includes depositing a contact etch stop layer (CESL) in the recess, wherein the CESL covers the implant region. The method further includes patterning the CESL to define a CESL block. The method further includes forming a waveguide and a grating in the substrate. The method further includes forming an interconnect structure over the waveguide, the grating and the CESL block. The method further includes etching the interconnect structure to define a cavity aligned with the grating.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a first dielectric layer, a work function layer, and a gate electrode sequentially stacked over the substrate, the first dielectric layer has a thin portion and a thick portion, the thin portion is thinner than the thick portion and surrounds the thick portion, and the first dielectric layer is a single-layer structure. The semiconductor device structure includes an insulating layer over the substrate and wrapping around the gate stack. The thin portion is between the thick portion and the insulating layer.

Abstract: Aspects of the subject disclosure may include, for example, a method in which a processing system detects user equipment (UE) in communication with a network via a serving cell of the network; the network is configured to facilitate communications by one or more terrestrial UEs and one or more aerial UEs. The system monitors messages from an aerial UE regarding detection of a cell other than the serving cell, and receives information from the aerial UE regarding the detected cell. The method further includes analyzing the information to estimate a first quantity associated with the detected cell location relative to the serving cell and a second quantity associated with a power received at the aerial UE from the detected cell. The method also includes determining, based on the analyzing, whether the aerial UE is an unauthorized aerial UE. Other embodiments are disclosed.

Abstract: A package structure includes a redistribution structure, a first semiconductor die, a first passive component, a second semiconductor die, a first insulating encapsulant, a second insulating encapsulant, a second passive component and a global shielding structure. The redistribution structure includes dielectric layers and conductive layers alternately stacked. The first semiconductor die, the first passive component and the second semiconductor die are disposed on a first surface of the redistribution structure. The first insulating encapsulant is encapsulating the first semiconductor die and the first passive component. The second insulating encapsulant is encapsulating the second semiconductor die, wherein the second insulating encapsulant is separated from the first insulating encapsulant. The second passive component is disposed on a second surface of the redistribution structure.

Abstract: A renewable energy generation system includes a renewable energy power generator including a capsule shape including a tumbling doll shape, floating on the sea, and producing electrical power by converting wave energy into electrical energy; a first hub connected to the renewable energy power generator and configured to store the electrical energy; and a cable configured to transmit the electrical energy produced by the renewable energy power generator to the first hub by connecting the renewable energy power generator to one or more of another renewable energy power generators and the first hub.