Patents Assigned to A&A Technologies
  • Patent number: 11487588
    Abstract: Techniques are provided for automatically resizing applications. In one technique, policy data that indicates an order of multiple policies is stored. The policies include (1) a first policy that corresponds to a first computer resource and a first resizing action and (2) a second policy that is lower in priority than the first policy and that corresponds to a second resizing action and a second computer resource. Resource utilization data is received from at least one application executing in a cloud environment. Based on the order, the first policy is identified. Based on the resource utilization data, it is determined whether criteria associated with the first policy are satisfied with respect to the application. If satisfied, then the first resizing action is performed with respect to the application; otherwise, based on the computer resource utilization data, it is determined whether criteria associated with the second policy are satisfied.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: November 1, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Abhishek Shivanna, Bharath Kumarasubramanian, Prateek Maheshwari, Rayman Preet Singh, Samarth Shetty, Kartik Paramasivam, Fan Xie, Pawas Chhokra, Sanil Jain
  • Patent number: 11487611
    Abstract: The present disclosure generally relates to applying LDPC coding to memory cells with an arbitrary number of levels. Modulation code is applied to a first portion of user bits. The coded user data is stored in a first modulation block. Parity bits are then generated for the first portion of user bits. The parity bits are then stored in a second modulation block different from the first modulation block. Modulation code is then applied to a second portion of user bits which are stored in the second modulation block. Parity bits are then generated for the second portion of user bits and stored in a third modulation block. The parity bits are thus embedded in a separate modulation block from the modulation block where the user data is stored.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: November 1, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Iouri Oboukhov, Richard Galbraith, Jonas Goode, Niranjay Ravindran
  • Patent number: 11490023
    Abstract: This disclosure is generally directed to mitigating light-emitting diode (LED) imaging artifacts in an imaging system of a vehicle. In an example embodiment, the imaging system includes a first camera that operates under control of a first pulse trigger sequence, and a second camera that operates under control of a second pulse trigger sequence. The second pulse trigger sequence has a temporal offset with respect to the first pulse trigger sequence. The first camera captures an image of a light source, such as a traffic light containing LEDs. This image may contain an LED imaging artifact indicating that the traffic light is off. The second camera also captures an image of the light source. The temporal offset of the second pulse trigger sequence may eliminate the LED imaging artifact in the second image. A controller may compare the two images and determine that the traffic light is actually on.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: November 1, 2022
    Assignee: Ford Global Technologies, LLC
    Inventor: David Herman
  • Patent number: 11487773
    Abstract: The present disclosure discloses a query method, an apparatus, an electronic device, and a storage medium, and relates to the technical field of spatio-temporal big data in big data technologies. The specific implementation scheme is as follows: receiving a query request sent by a terminal device, where the query request is used to request to query dynamic association relationships of a target entity and includes an identifier of the target entity and query starting and ending time; determining at least one time bucket to be queried in a query database according to the query starting and ending time, where each time bucket stores the dynamic association relationships of the target entity in a time period corresponding to the time bucket; and querying the dynamic association relationships of the target entity in the at least one time bucket according to the identifier of the target entity.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: November 1, 2022
    Assignee: BEIJING BAIDU NETCOM SCIENCE TECHNOLOGY CO., LTD.
    Inventors: Shuangquan Yang, Yang Zhang, Yi Xie
  • Patent number: 11485665
    Abstract: A pair of moulds for moulding an optical component is disclosed. The pair of moulds includes a first mould having a first surface, and a second mould having a second surface. The first surface includes a moulding portion for moulding a first optical surface of the optical component, and an alignment portion for alignment with the second mould. The alignment portion extends around the moulding portion. The second surface includes a moulding portion for moulding a second, opposite optical surface of the optical component, and an alignment portion for alignment with the first mould via a contact with the alignment portion of the first surface. When the moulds are brought together, they self-align. A corresponding moulding apparatus and a method may use the mould pair to manufacture various optical components.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: November 1, 2022
    Assignee: Meta Platforms Technologies LLC
    Inventors: Kurt Jenkins, Michael Patrick Schaub, Byron Taylor
  • Patent number: 11490495
    Abstract: An LED sticker is disclosed that receives an NFC transmission from a nearby smartphone to energize LEDs in the sticker. A spiral (or loop) antenna is used in the sticker to generate power from the NFC transmission. The NFC signal is at 13.56 MHz, which is the resonant frequency of the NFC antenna circuit in the smartphone. The LED portion is formed by sandwiching pre-formed microscopic LEDs between two conductive layers to connect the LEDs in parallel. The conductive layers form a relatively large integral capacitor that is used to achieve the 13.56 MHz resonant frequency. So no additional capacitor is needed in the circuit to achieve a resonance of 13.56 MHz. This greatly reduces the design requirements of the antenna. The LED sticker may also contain an NFC tag having its own independent loop antenna and NFC chip. Various practical applications of the LED sticker are disclosed.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: November 1, 2022
    Assignee: NthDegree Technologies Worldwide, Inc.
    Inventors: Rodger Whitby, Bradley S. Oraw
  • Patent number: 11487526
    Abstract: Methods and systems for providing distributed user agent information updating. One system includes a data processing server configured to receive an update event associated with an update to an active version of user agent information. The active version of the user agent information is actively accessible for request enrichment. The data processing server is also configured to generate an updated version of the user agent information according to the update and replace the active version with the updated version in storage. In response to the storage of the updated version, the updated version is actively accessible for request enrichment.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: November 1, 2022
    Assignee: MASTERCARD TECHNOLOGIES CANADA ULC
    Inventors: Justine Celeste Fox, Marc Grimson
  • Patent number: 11489060
    Abstract: The present application provides a semiconductor device with an air gate spacer for reducing parasitic capacitance and a method for manufacturing the semiconductor device. The semiconductor device includes a stacking structure, a first sidewall spacer and a second sidewall spacer. The stacking structure stands on a semiconductor substrate. The first and second sidewall spacers cover a sidewall of the stacking structure. An air gap is sealed between the first and second sidewall spacers. A top end of the air gap is substantially aligned with top ends of the first and second sidewall spacers. A top portion of the air gap is tapered toward a top end of the air gap.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: November 1, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11489433
    Abstract: A method for driving an electronic switch in a power converter and a power converter are disclosed. The method includes: driving an electronic switch (1) coupled to an inductor (2) in the power converter, wherein driving the electronic switch (1) includes driving the electronic switch (1) in a plurality of drive cycles by a drive signal (SDRV), Driving the electronic switch (1) in at least one of the plurality of drive cycles includes: determining a desired duration (TON_DES) of a current (I1) through the switch (1); and adjusting a duration (TDRV) of an on-level of the drive signal (SDRV) dependent on the desired duration (TON_DES) and a delay time (TDEL) obtained in a preceding drive cycle. The delay time (TDEL) is a time duration, in the preceding drive cycle, between a first time instance (t1) when the drive signal (SDRV) changes from the on-level to an off-level and a second time instance (t2) when a current through the electronic switch (1) falls below a predefined threshold.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: November 1, 2022
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Feldtkeller
  • Patent number: 11489090
    Abstract: The present disclosure describes epitaxial oxide field effect transistors (FETs). In some embodiments, a FET comprises: a substrate comprising an oxide material; an epitaxial semiconductor layer on the substrate; a gate layer on the epitaxial semiconductor layer; and electrical contacts. In some cases, the epitaxial semiconductor layer can comprise a superlattice comprising a first and a second set of layers comprising oxide materials with a first and second bandgap. The gate layer can comprise an oxide material with a third bandgap, wherein the third bandgap is wider than the first bandgap. In some cases, the epitaxial semiconductor layer can comprise a second oxide material with a first bandgap, wherein the second oxide material comprises single crystal AxB1-xOn, wherein 0<x<1.0, wherein A is Al and/or Ga, wherein B is Mg, Ni, a rare earth, Er, Gd, Ir, Bi, or Li.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: November 1, 2022
    Assignee: Silanna UV Technologies Pte Ltd
    Inventor: Petar Atanackovic
  • Patent number: 11488643
    Abstract: A system comprises an interposer including multiple conductive interconnects; multiple chiplets arranged on the interposer and interconnected by the interposer; each chiplet including a die-to-die physical layer interface including one or more pads to engage the interconnect of the interposer; and wherein at least one chiplet includes multiple input-output channels organized into at least one column and arranged in an order at a periphery of the chiplet forming a die-to-die physical layer interface to engage the interconnects of the interposer, wherein the order of the channels of the column is programmable.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: November 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Dean E. Walker, Tony Brewer
  • Patent number: 11485302
    Abstract: Systems and methods are provided herein for adjusting vehicle features based on user preferences and physical dimensions. In some embodiments, the systems and methods described herein may more particularly relate to the automated adjustment of vehicle features such as, for example, seat positioning and mirror positioning, without requiring input from a user.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: November 1, 2022
    Assignee: Ford Global Technologies, LLC
    Inventors: Brendan Diamond, Erik J. Christen
  • Patent number: 11487415
    Abstract: An interactive and automated summarized schedule on a digital canvas includes a hierarchy of logic-tied schedule densities generated from source schedule activities and for which there is the ability in real-time to zoom in/out among the hierarchy of logic-tied schedule densities. For example, the hierarchy of logic-tied schedule densities is generated in response to and as the timescale (e.g., grid spacing) is compressed or stretched. This permits users to “zoom in” and “zoom out” on the digital canvas to observe the schedule activities individually or at various levels of summary groups that are summed-up from underlying individual activities, all while maintaining logic-relationships between the summarized groups.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: November 1, 2022
    Assignee: PMA TECHNOLOGIES, LLC
    Inventors: Gui Ponce de Leon, Vivek Puri, Seve Ponce de Leon, Sergio Ponce de Leon
  • Patent number: 11487469
    Abstract: An apparatus controls access to a memory module coupled to a host controller via a data bus to exchange data with the host controller. The apparatus has a configurable information memory and comprises: an access control input port via which the apparatus receives a data access command from the host controller; a control unit to identify a data access command including an access address directed to a predetermined storage region of the memory module, and generate an information processing command based at least on the access address directed to the predetermined storage region, such that the control unit can configure the information memory based on the information processing command or provide the information processing command to the memory module; and an access control output port via which the apparatus provides the information processing command to the memory module, such that the memory module outputs corresponding data information to the host controller based on the information processing command.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: November 1, 2022
    Assignee: MONTAGE TECHNOLOGY CO., LTD.
    Inventors: Yi Li, Gang Shan, Howard Chonghe Yang
  • Patent number: 11484982
    Abstract: An online geometric/thermal error measurement and compensation system for computer numerically controlled (CNC) machine tools belonging to the technical field of error testing and compensation of CNC machine tools. The online CNC machine tool geometric/thermal error measurement and compensation system includes two parts: the hardware platform and the measurement and compensation software. The hardware platform includes a unidirectional acceleration sensor, a precision integrated circuit (IC) temperature sensor, a multi-channel temperature data collector, and a geometric/thermal error measurement and compensation host. The error measurement and compensation software runs in the geometric/thermal error measurement and compensation host and realizes testing and compensation of geometric and thermal errors in machine tools, which are communicated to the FANUC CNC system.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: November 1, 2022
    Assignee: DALIAN UNIVERSITY OF TECHNOLOGY
    Inventors: Kuo Liu, Te Li, Yongquan Gan, Wei Han, Dawei Li, Zhisong Liu, Yongqing Wang
  • Patent number: 11486037
    Abstract: A method of fabricating a plurality of single crystal CVD diamonds. The method includes mounting a plurality of single crystal diamond substrates on a first carrier substrate. The plurality of single crystal diamond substrates is subjected to a first CVD diamond growth process to form a plurality of single crystal CVD diamonds on the plurality of single crystal diamond substrates. The plurality of single crystal CVD diamonds are mounted in a recessed carrier substrate and subjected to a second CVD diamond growth process.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: November 1, 2022
    Assignee: Element Six Technologies Limited
    Inventors: Ben Llewelyn Green, Andrew Michael Bennett, Timothy Peter Mollart, Stefan Ian Olsson Robbie
  • Patent number: 11484000
    Abstract: The invention relates to the soybean variety designated 01083661. Provided by the invention are the seeds, plants and derivatives of the soybean variety 01083661. Also provided by the invention are tissue cultures of the soybean variety 01083661 and the plants regenerated therefrom. Still further provided by the invention are methods for producing soybean plants by crossing the soybean variety 01083661 with itself or another soybean variety and plants produced by such methods.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: November 1, 2022
    Assignee: MONSANTO TECHNOLOGY, LLC
    Inventor: Jeffrey Tyler
  • Patent number: 11484706
    Abstract: Apparatus is provided for treating an intervertebral disc of a subject, the apparatus including: at least one intra-pulposus exposed electrode surface, which is configured to be implanted in a nucleus pulposus of the intervertebral disc; and one or more extra-pulposus exposed electrode surfaces, which are configured to be implanted outside the nucleus pulposus, in electrical communication with the intervertebral disc. Control circuitry is electrically coupled to the at least one intra-pulposus exposed electrode surface and one or more extra-pulposus exposed electrode surfaces. The control circuitry is configured to drive fluid and introduce nutritional substances into the intervertebral disc, by applying a voltage between the at least one intra-pulposus exposed electrode surface and the one or more extra-pulposus exposed electrode surfaces. Other embodiments are also described.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: November 1, 2022
    Assignee: Discure Technologies Ltd
    Inventors: Yossi Gross, Gideon Fostick
  • Patent number: D968253
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: November 1, 2022
    Assignee: Hangzhou Meari Technology Co., Ltd.
    Inventors: Chao Qin, Davy Ying
  • Patent number: D968416
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: November 1, 2022
    Assignee: DONGGUAN RUNBONE TECHNOLOGY CO., LTD
    Inventor: Zhi Pan