Abstract: The systems and methods of the present invention provide a solution that makes data provably secure and accessible—addressing data security at the bit level—thereby eliminating the need for multiple perimeter hardware and software technologies. Data security is incorporated or weaved directly into the data at the bit level. The systems and methods of the present invention enable enterprise communities of interest to leverage a common enterprise infrastructure. Because security is already woven into the data, this common infrastructure can be used without compromising data security and access control. In some applications, data is authenticated, encrypted, and parsed or split into multiple shares prior to being sent to multiple locations, e.g., a private or public cloud. The data is hidden while in transit to the storage location, and is inaccessible to users who do not have the correct credentials for access.

Abstract: A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module.

Abstract: The present invention provides an integrated inductor and an integrated inductor fabricating method. The integrated inductor comprises: a semiconductor substrate, an inductor, and a redistribution layer (RDL). The inductor is formed above the semiconductor substrate. The RDL is formed above the inductor and has a specific pattern to form a patterned ground shield (PGS). The integrated inductor fabricating method comprises: forming a semiconductor substrate; forming an inductor above the semiconductor substrate; and forming redistribution layer (RDL) having a specific pattern above the inductor to form a patterned ground shield (PGS).

Abstract: A method for fabricating a semiconductor device, and a semiconductor device made with the method are described. In the method, a cavity is formed in a substrate, a first epitaxy process is performed under a pressure higher than 65 torr to form a buffer layer in the cavity, and a second epitaxy process is performed to form a semiconductor compound layer on the buffer layer in the cavity. In the semiconductor device, the ratio (S/Y) of the thickness S of the buffer layer on a lower sidewall of the cavity to the thickness Y of the buffer layer at the bottom of the cavity ranges from 0.6 to 0.8.

Abstract: The present invention relates to an expansion chassis for a laptop computer. Specifically, the expansion chassis provides additional expansion bays for increased functionality, storage and/or battery power for the laptop computer. One or more BUS multipliers are integrated into a native SATA BUS, and one or more multifunction USB interconnect cables are integrated therein to integrate the expansion chassis into the existing laptop functions.

Abstract: A hinge structure is provided. The hinge structure includes a fixing base, a pivot unit and a supporting element. The pivot unit includes a shaft, wherein the shaft passes through the fixing base, and the shaft is moved in a predetermined direction between a first shaft position and a second shaft position relative to the fixing base, and the predetermined direction is perpendicular to an extending direction of the shaft. The supporting element includes a first connection portion and a second connection portion, wherein the first connection portion and the second connection portion are respectively located at two ends of the supporting element, and the second connection portion pivots on the shaft.

Abstract: A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.

Abstract: A circuit includes an input dispatch unit for receiving an input signal and a calibration signal and outputting N dispatched signals in accordance with a selection signal. The circuit also includes N analog-to-digital converter (ADC) units for receiving the N dispatched signals, N control signals, and N mapping tables and outputting N raw data, and N refined data, respectively. An output dispatch unit receives the N refined data and outputting an output data in accordance with the selection signal, and a calibration controller receives the N raw data and outputting the selection signal, the N control signals, the N mapping tables, and a digital code. A DAC (digital-to-analog converter) receives the digital code and outputting the calibration signal, wherein one of the dispatched signals, as specified by the selection signal is from the calibration signal while the other dispatched signals are from the input signal.

Abstract: Stand assembly includes base and first and second stand units. The first stand unit includes first body and extending portion. The first body has first and second ends and first shaft. The extending portion connects the first body and has first shaft hole having first hole portion and second hole portion communicated with each other. The first shaft is pivotally connected to the base. The second stand unit includes second body having third end and second shaft. The second shaft is pivotally connected to the first or second hole portion, selectively. When the second shaft is pivotally connected to the first hole portion, the third end abuts against the second end. When the second shaft is pivotally connected to the second hole portion, the third end leaves the second end, so the second stand unit can rotating relative to the first stand unit.

Abstract: The optical proximity correction verification method includes loading a layout data to be verified to a processor, loading a reference layout data to the processor. The processor performs a first stage Boolean operation on the layout data to be verified to generate first verified data. The processor performs a layout versus layout verification on the first verified data to generate second verified data by using the reference layout data. If the layout versus layout verification is successfully performed, the processor performs a second stage Boolean operation on the second verified data to generate third verified data. By using the reference layout data, the processor performs a Boolean check on the third verified data to generate fourth verified data.

Abstract: A device for processing media may include a system and method for loading and unloading consumable supplies of a printer, and more particularly, a system and method for providing a compact form factor printer which provides convenient access to the replaceable components of the printer. A printer may include a base and a lid hingedly attached to the base, moveable between a closed position in which the lid is secured to the base, and an open position. A cavity may be defined between the lid and the base, where the cavity is inaccessible when the lid is in the closed position and the cavity is accessible when the lid is in the open position. The printer may include a ribbon positioning assembly disposed within the cavity.

Abstract: A pixel structure of an electroluminescent display panel includes display pixel units. Each display pixel unit is composed of one first sub-pixel, one second sub-pixel, and one third sub-pixel. Each first sub-pixel is disposed adjacent to another first sub-pixel along a column direction to form a first pixel unit with a first frame. Each second sub-pixel is disposed adjacent to another second sub-pixel along the column direction to form a second pixel unit with a second frame. Each third sub-pixel is disposed adjacent to another third sub-pixel along the column direction to form a third pixel unit with a third frame. Each first, second, and third pixel units respectively have an identical first length along the column direction. Each first pixel unit and one adjacent first pixel unit disposed in a different row are shifted relatively along the row direction by the first length.

Abstract: A powered device interface arranged as an interface between power received over a structured communication cabling and a powered device, the powered device interface constituted of: a class event counter; a logic circuit in communication with the class event counter; and a plurality of flag outputs each responsive to the logic circuit, each of the flag outputs associated with a predetermined powering level of a power sourcing equipment connected over the structured communication cabling, the logic circuit arranged to: output an active signal at the flag output associated with a detected powering level of the connected power sourcing equipment; and output an active signal at all other flag outputs associated with powering levels less than the detected powering level of the connected power sourcing equipment.

Abstract: A method of forming a contact hole includes providing a substrate. A nitrogen-containing dielectric layer, a first material layer, a second material layer, an oxygen-containing dielectric layer and a patterned photoresist layer cover the substrate from bottom to top. Then, the oxygen-containing dielectric layer is etched by taking the second material layer as a first etching stop layer to form a patterned oxygen-containing dielectric layer. Latter, the second material layer is etched by taking the first material layer as a second etching stop layer to form a patterned second material layer. Subsequently, the first material layer is etched by taking the nitrogen-containing dielectric layer as a third etching stop layer to form a patterned first material layer. Finally, the nitrogen-containing dielectric layer is etched until the substrate is exposed.

Abstract: A memory cell structure is provided. A first doping region is formed in a substrate. A second doping region is formed in the substrate. A first gate is formed on the substrate. The first and second doping regions and the first gate constitute a first transistor. A first word line is electrically connected to the first gate. The first word line firstly extends along a first direction and then along a second direction which is different from the first direction. A resistive layer is electrically connected to the first doping region. A conductive layer comprises a first source line and a bit line. The first source line is electrically connected to the second doping region, and the bit line is electrically connected to the resistive layer. The first and second doping regions extend along a third direction which is different from the first and second directions.

Abstract: Disclosed are a locking unit and a G-sensor assembly for a vehicle tray using the locking unit. The locking unit may include a case unit fixed to a first object and a magnetic assembly for selectively engaging with a second object which is disposed outside the case unit. The magnetic assembly may be movably disposed in the case unit. When a shock is generated, the magnetic assembly may move from inside the case unit to outside the case unit by a repulsive force generated between magnets having a same polarity, and consequently engage with the second object and restrict rotation of the second object.

Abstract: The present invention provides Bruton's Tyrosine Kinase (Btk) inhibitor compounds according to Formula I or a pharmaceutically acceptable salt thereof or to pharmaceutical compositions comprising these compounds and to their use in therapy. In particular, the present invention relates to the use of Btk inhibitor compounds in the treatment of Btk mediated disorders.