Patents Assigned to A + Corp.
  • Publication number: 20040188254
    Abstract: Methods and systems that employ hybrid fluid flow profiles for optimized movement of materials through channel networks. These systems employ hybrid pressure-based and electrokinetic based flow systems for moving materials through interconnected channel networks while maintaining interconnection among the various channel segments. In particular, the invention is generally directed to channel networks where flow in a first channel segment is driven by pressure flow with its consequent parabolic flow profile, while flow in an interconnected channel segment is dominated by electrokinetic flow with its consequent plug flow profile. The invention also provides channel networks wherein fluid flow in channel segments is driven by both pressure and electric field and the multiple species contained in a fluid plug are separated (and can be concentrated) by altering the applied pressure and electric fields in the various channel segments of the channel networks.
    Type: Application
    Filed: December 22, 2003
    Publication date: September 30, 2004
    Applicant: Caliper Technologies Corp.
    Inventor: Michael Spaid
  • Publication number: 20040189842
    Abstract: An AD-converted digital video data is encoded by a difference encoding method before it is outputted and such encoded digital video data is then outputted, after it is converted to gray code or to a predetermined code in which a fixed value is added. Problems solved include noise that is generated when the AD conversion circuit outputs video data and that migrates into a CCD side via a power supply line on a printed circuit board, and noise that appears on a display image by migration into an input terminal side from an output circuit side via the power supply line and a semiconductor substrate within an AD conversion LSI.
    Type: Application
    Filed: April 5, 2004
    Publication date: September 30, 2004
    Applicants: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Yasutoshi Aibara, Hiroki Nakajima, Eiki Imaizumi, Tatsuji Matsuura
  • Publication number: 20040192047
    Abstract: A method of pre-etching a glass substrate for reducing a post-releasing time is provided. The method includes steps of: The glass substrate, a micro-structure and a silicon substrate are provided. The glass substrate is connected with the micro-structure. A first etching process is performed on the glass substrate for reducing the area of the glass substrate connected with the micro-structure. The micro-structure is connected with the silicon substrate and a second etching process is performed on the glass substrate for removing the micro-structure from the glass substrate.
    Type: Application
    Filed: March 3, 2004
    Publication date: September 30, 2004
    Applicant: Walsin Lihwa Corp.
    Inventors: Long-Sun Huang, Bing-Ru Chen, Shi-Yuan Tseng
  • Publication number: 20040190352
    Abstract: A main control circuit generates a plurality of main control signals of different phases to local control circuits. The local control circuits produce row-related control signals greater in number than the main control signals in accordance with these main control signals.
    Type: Application
    Filed: April 13, 2004
    Publication date: September 30, 2004
    Applicants: RENESAS TECHNOLOGY CORP., MITSUBISHI ELECTRIC ENGINEERING COMPANY LIMITED
    Inventors: Naoya Watanabe, Aiko Nishino, Katsumi Dosaka
  • Publication number: 20040193756
    Abstract: The serial communication device capable of reducing the load on the CPU is provided for a system using the serial communications such as the car navigation system. The attention is focused on the control method of the serial communication, in which a DMA controller is used for the data reception in the serial communication, and a number larger than the number of data received at a time is set in advance as the number of transfers of the receive DMA controller, and further, the function to generate the timeout interrupt when data is not received for a certain period is added to the serial interface, so that the serial communication can be controlled and performed without applying the load on the CPU.
    Type: Application
    Filed: March 25, 2004
    Publication date: September 30, 2004
    Applicants: Renesas Technology Corp., Alpine Electronics, Inc.
    Inventors: Kenji Kamada, Yoichi Onodera, Yasumasa Suzuki
  • Publication number: 20040188245
    Abstract: A metal coil or an elastic cushion formed by winding the metal coil around a corrosion-resistant frame is sandwiched between an electrode and an electrode collector or a cell wall or is used as an electrode. The elasticity of the metal coil or the elastic cushion enables the easy handling and the uniform contact between the electrode and another electrolysis element. The metal coil or the elastic cushion can be also used as an elastic cathode. The elasticity of the elastic cathode also enables the easy handling of the electrode itself and the uniform contact between the ion exchange membrane and the current collector.
    Type: Application
    Filed: March 30, 2004
    Publication date: September 30, 2004
    Applicant: CHLORINE ENGINEERS CORP., LTD.
    Inventors: Shinji Katayama, Kiyohito Asaumi
  • Publication number: 20040189847
    Abstract: A lightweight, portable magnification system for magnified inspection of an object. The magnification system has a compact housing constructed for supporting components of the magnification system, a display mounted on the housing for viewing a magnified image of the object to be inspected, and a camera carried by the housing.
    Type: Application
    Filed: January 30, 2004
    Publication date: September 30, 2004
    Applicant: Dazor Manufacturing Corp.
    Inventors: Mark C. Hogrebe, E. William Binder, Darryl W. Eschmann, Wayne T. Wickerham
  • Publication number: 20040188139
    Abstract: A method of manufacturing a wiring circuit board having bumps is disclosed in which a stable bump connection is possible, and complex operations such as plating pre-treatment are unnecessary. Bumps having a surface roughness on the tip face thereof of 0.2 to 20 &mgr;m are formed by forming an etching mask for bump formation on bump formation surface of a metal foil which has a thickness (t1+t2) which is the sum of a thickness t1 of a wiring circuit and a height t2 of bumps to be formed on wiring circuit and which has a surface roughness of the bump formation surface thereof of 0.2 to 20 &mgr;m, and half etching the metal foil from the side of the etching mask for bump formation to a depth corresponding to the desired bump height t2.
    Type: Application
    Filed: April 7, 2004
    Publication date: September 30, 2004
    Applicant: Sony Chemicals Corp.
    Inventor: Yutaka Kaneda
  • Publication number: 20040191727
    Abstract: An implant includes an implantable body portion adapted to be at least partially recessed within a patient's alveolar bone, and which has a peripheral surface portion which is configured to stimulate and/or facilitate the engagement of osteoblasts and other bone tissues with the implant. The implant body provides bone engaging regions along one or more of the distal and/or mesial implant surfaces which are elongated relative to bone engaging regions on the lingual and/or buccal surfaces of the implant body. In particular, the implantable portion of the implant body includes a bone engaging surface which, when the implant body is fully seated within the patient's jaw bone, extends from a distal portion of the implant body to a remote proximal-most edge. The proximal-most edge has a contour selected to generally follow a predetermined crestal outline of the supporting bone tissue.
    Type: Application
    Filed: January 8, 2004
    Publication date: September 30, 2004
    Applicant: Innova Corp.
    Inventors: Avi Shelemay, Mike Kehoe
  • Publication number: 20040189534
    Abstract: A tri-band antenna and method for forming the same are disclosed. The antenna comprises a meander line radiator, a tapered line radiator coupled to the meander line radiator, a straight line radiator coupled to the tapered line radiator, and a dielectric layer. Exemplary meander line, tapered line, and straight line radiators are formed as microstrip structures overlying the dielectric layer surfaces. According to one embodiment, the meander line radiator is formed on the dielectric top surface and is connected to the tapered line radiator on the dielectric bottom surface through a via. The straight line radiator is connected to the tapered line radiator output on the bottom surface, and is unterminated. In one aspect, the combination of the meander line radiator, tapered line radiator, and straight line radiator forms effective electrical lengths corresponding to the cellular frequency band, the GPS frequency band, and the PCS frequency band.
    Type: Application
    Filed: April 5, 2004
    Publication date: September 30, 2004
    Applicant: KYOCERA WIRELESS CORP.
    Inventor: Jatupum Jenwatanavet
  • Publication number: 20040194044
    Abstract: A datapath extraction unit extracts, from among datapaths on which a timing verification is to be performed, those datapaths from a netlist, timing constraints, and a cell library, that are established between at least two child blocks of a parent block. A datapath output unit prepares and presents to the user a datapath list in which timing exceptions can be specified. A timing constraints modification unit modifies the previous timing constraints according to the timing exceptions specified by the user and creates new timing constraints.
    Type: Application
    Filed: July 11, 2003
    Publication date: September 30, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventor: Genichi Tanaka
  • Publication number: 20040193291
    Abstract: A production management method includes the steps of: pre-storing production information including delivery date information, manufacturing apparatus information and lot information; calculating a scheduled shipping date for each lot on the basis of the production information; reading a delivery date of the lot; calculating the number of delay days of the lot; outputting an alarm to the lot when the number of delay days is a positive number; and analyzing the main cause of the delay of the lot and generating an expedite instruction when the number of delay days is larger than 1.
    Type: Application
    Filed: September 23, 2003
    Publication date: September 30, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventor: Akiko Sakai
  • Publication number: 20040189898
    Abstract: A reflective liquid crystal display disclosed herein includes a transistor substrate, a color filter substrate, a first lower electrode, a first upper electrode, a first transparent insulator, a second transparent insulator, a second lower electrode, a second upper electrode and a liquid crystal layer. The first lower electrode, the first transparent insulator and the second lower electrode are formed sequentially on the top surface of the transistor substrate. The first upper electrode, the second transparent insulator and the second upper electrode are fabricated sequentially on the bottom surface of the color filter substrate. The liquid crystal layer is sandwiched between the second lower electrode and the second upper electrode. One of the first lower electrode and the second lower electrode is electrically connected to a plurality of transistors and reflects the external light.
    Type: Application
    Filed: March 26, 2004
    Publication date: September 30, 2004
    Applicant: Toppoly Optoelectronics Corp.
    Inventor: Chaung-Chi Wang
  • Publication number: 20040193928
    Abstract: Disclosed herewith is a semiconductor processing system such as a card type electronic device, which can easily cope with an error caused by power shutoff that occurs when the card is ejected. The semiconductor processing system is provided with an interface control circuit and a processing circuit and receives operation power from an external device such as a card slot when it is inserted therein. According to a first aspect of the present invention for coping with an error caused by power shutoff that occurs when the card is ejected, the interface control circuit, when the card is ejected from the card slot, detects a potential change to occur at a first external terminal to be disconnected from a predetermined terminal of the card slot before the power supply from the card slot is shut off, then instructs the processing circuit that is active to perform an ending processing. The semiconductor processing system can end the processing by itself before the power supply stops completely.
    Type: Application
    Filed: November 17, 2003
    Publication date: September 30, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Shinichi Shuto, Takayuki Tamura, Chiaki Kumahara
  • Publication number: 20040189716
    Abstract: A system and method that enables a designer to build electronic forms and corresponding hierarchical schemas are described. Displays of hierarchical schemas, electronic forms, and components used to build the hierarchical schemas and electronic forms are provided to the designer. The designer selects components and arranges them on a display to visually build an electronic form. As the form is built, the corresponding hierarchical schema is incrementally updated to reflect changes made to the electronic form.
    Type: Application
    Filed: March 24, 2003
    Publication date: September 30, 2004
    Applicant: MICROSOFT CORP.
    Inventors: Jean D. Paoli, Laurent Mollicone, Ned B. Friend, Matthew J. Kotler, Thomas R. Lawrence, Shuk-Yan Lai, Sharma K. Hendel, Jason Whitmarsh
  • Publication number: 20040192009
    Abstract: A trench isolation structure is formed in a substrate. One or more openings are formed in a surface of the substrate, and a liner layer is deposited at least along a bottom and sidewalls of the openings. A layer of doped oxide material is deposited at least in the openings, and the substrate is annealed to reflow the layer of doped oxide material. Only a portion near the surface of the substrate is removed from the layer of doped oxide material in the opening. A cap layer is deposited atop a remaining portion of the layer of doped oxide material in the opening.
    Type: Application
    Filed: March 26, 2003
    Publication date: September 30, 2004
    Applicants: Infineon Technologies North America Corp., International Business Machines Corporation
    Inventors: Michael Belyansky, Andreas Knorr, Oleg Gluschenkov, Christopher Parks
  • Publication number: 20040190672
    Abstract: A bi-directional shift-register circuit for outputting data in different sequence. A first shift-register unit includes a first-stage control terminal and a first-stage output terminal outputs a first output signal. A second shift-register unit includes a second-stage input terminal coupled to the first-stage output terminal and a third-stage output terminal, a second-stage control terminal and a second-stage output terminal outputs a second output signal. The second-stage control terminal is selectively coupled to the first-stage output terminal and the third-stage output terminal and disables the second shift-register unit according to the first output signal or a third output signal. A third shift-register unit includes a third-stage control terminal and the third-stage output terminal outputs the third output signal.
    Type: Application
    Filed: June 5, 2003
    Publication date: September 30, 2004
    Applicant: AU Optronics Corp.
    Inventors: Shi-Hsiang Lu, Jian-Shen Yu
  • Publication number: 20040190315
    Abstract: D.C.-A.C. converting circuit capable of increasing boosting efficiency and reducing noise, including a boosting section composed of serially connected transistors, inductors and capacitors and an A.C. electronic switch part composed of several transistors (electronic switches such as MOSFET, gate throttle, etc.) and capacitors. When the signal for controlling the operation of the transistors is boosted from low potential to high potential, the operation of the transistors is speeded. When cut off, the signal is formed with a negative voltage level pattern, whereby the transistors can be more quickly cut off. The electronic switch part of the circuit is replaceable with several serially connected diodes to also achieve the voltage for increasing boosting efficiency. During discharge, a measure for controlling the current of the circuit is added so as to reduce the noise produced during boosting procedure.
    Type: Application
    Filed: March 26, 2003
    Publication date: September 30, 2004
    Applicant: SEMISILICON TECHNOLOGY CORP.
    Inventor: Jacky Peng
  • Publication number: 20040190086
    Abstract: A multi-function peripheral (MFP) includes a built-in video encoder. Through the video encoder, an image data can be directly displayed on the large-size screen of a TV or computer monitor, and an user can then preview, select and process the image data thereon. The MFP may also include one or more I/O interfaces used to connect other commercially available electronic devices.
    Type: Application
    Filed: March 22, 2004
    Publication date: September 30, 2004
    Applicant: Realtek Semiconductor Corp.
    Inventors: Ming-Yuh Yeh, Jyh-Kwang Chen, Hui-Huang Chang
  • Publication number: 20040193858
    Abstract: A loop instruction, at least one target instruction, and an associated trigger address are cached during loop entry. During each loop iteration, the processor predicts whether the loop will be taken or not-taken in a subsequent iteration. When pre-fetch of the cached loop instruction is subsequently detected (i.e., by comparing the trigger address with the current program counter value), the loop taken/not-taken prediction is used to fetch either loop body instructions (when predicted taken) or fall-through instructions (when predicted not-taken). The cached loop instruction is then executed and the loop taken/not-taken prediction is verified using a dedicated loop execution circuit while a penultimate loop body instruction is executed in the processor execution stage (pipeline). When a previous loop taken prediction is verified, the cached target instruction is executed, and then the fetched loop body instructions are executed.
    Type: Application
    Filed: March 24, 2003
    Publication date: September 30, 2004
    Applicant: Infineon Technologies North America Corp.
    Inventors: Sagheer Ahmad, Matthias Knoth, Roger D. Arnold