Abstract: A system and method for jitter injection is provided. The system may include a serializer-deserializer (SerDes) circuit. In some examples, the serializer-deserializer (SerDes) circuit have a pre-emphasis circuit and a post emphasis circuit. The system may also include a controller, which may be used to apply specific and varying amounts of pre-emphasis and post-emphasis. The system may also include a jitter injector. In some examples, the jitter injector may be used to inject jitter into the serializer-deserializer (SerDes) circuit based on the applied pre-emphasis and post-emphasis.

Abstract: A system and method for jitter injection is provided. The system may include a serializer-deserializer (SerDes) circuit. In some examples, the serializer-deserializer (SerDes) circuit have a pre-emphasis circuit and a post emphasis circuit. The system may also include a controller, which may be used to apply specific and varying amounts of pre-emphasis and post-emphasis. The system may also include a jitter injector. In some examples, the jitter injector may be used to inject jitter into the serializer-deserializer (SerDes) circuit based on the applied pre-emphasis and post-emphasis.

Abstract: A dynamically reconfigurable interface for an automatic test equipment is disclosed where one or more synthetic instruments transmit the high speed signals as well as receive the high speed signals from a device under test so that testing can be performed at speeds higher than the ATE was originally designed to accommodate. Synthetic instruments are implemented on a field programmable gate array (FPGA) that operate at higher speeds than COTS instruments and can reach the frequencies that high speed I/O buses use. SIs can be created by configuring the FPGA, with different configurations creating different SIs. A single FPGA can house a number of SIs.

Abstract: Universal test apparatus for automatically testing electric circuits. A host computer communicates with the apparatus through a first interface. A unit under test communicates with the apparatus through a second interface. The apparatus has a plurality of multifunctional storage registers. Responsive to commands from the host computer the individual registers are alternatively configured to receive drive signals through the first interface from the host computer, to receive response signals through the second interface from the unit under test, to receive signals transferred from another register, and to transfer signals to another register. Drive signals stored in a register transmitted to the unit under test and response signals stored in a function of the host computer is performed by one or more microprocessors which comprise part of the electric circuits being tested.