Abstract: Embodiments of the present disclosure provide methods and integrate circuits with dynamic phase alignment between an input data signal and a clock signal. In some embodiments, a sampling window of the input data signal may be determined and timing of the input data signal may be adjusted to enable the input data signal to be sampled within the sampling window. Other embodiments may be disclosed and claimed.

Abstract: Embodiments provide input/output devices having programmable logic that is programmable to operate input/output devices in one of two drive modes. In various embodiments, to operate an input/output device in a first drive mode, logic circuitry is programmable to couple a reference voltage to a gate of a transistor element of an output driver. In various embodiments, to operate an input/output device in a second drive mode, the logic circuitry is programmable to couple a bias voltage to the gate of the transistor element of the output driver. In various embodiments, the logic circuitry may also be programmable to couple one of a plurality of data inputs to the output driver to operate an input/output device in either a single-ended mode or a differential mode.

Abstract: An integrated circuit (IC) includes a number of function blocks (FB), of which at least one is re-configurable. Each of the FBs may be a reconfigurable function or a non-reconfigurable function or recursively expanded with additional “nested” function blocks. The IC further includes a number of input pins, a number of output pins, an adder, and a number of crossbar devices. The elements, at least at the IC level, are coupled in a manner such that all input signals are provided to the FBs through a first subset of the crossbar devices, all internal signals are routed from one FB to another FB through a second subset of crossbar devices, and all output signals are routed from the FBs to the output pins through a third subset of crossbar devices. To increase routability and speed each of the crossbar device output has a single fanout. Additionally, each of the crossbar devices may provide only one input to each other crossbar device.

Abstract: Reconfigurable circuits, methods, and systems with reconfigurable interconnect devices, clusters of reconfigurable logic devices, and a programming interface configured to receive configuration data to configure a first combination of the reconfigurable interconnect and logic devices to implement a circuit, and to remap a portion of the received configuration data, corresponding to a defective cluster, from the defective cluster to another non-defective cluster of the plurality of clusters to configure a second combination of the reconfigurable interconnect and logic devices to implement the circuit.