Abstract: A substrate with an embedded element includes a core substrate having one surface and a cavity recessed from the one surface in a thickness direction; an element package disposed in the cavity, the element package comprising one or more elements; and a substrate insulating material surrounding at least part of the element package. When observed from a side surface of the substrate with the embedded element, the substrate with the embedded element includes a cavity area in which the cavity is disposed and a substrate area outside of the cavity area. An absolute value of difference between an average thickness of the substrate area and an average thickness of the cavity area is 50 ?m or less.

Abstract: A substrate comprising a glass substrate is provided. The glass substrate includes a first surface, a second surface, and an edge area connecting the first surface and the second surface; a groove part formed toward the inside direction of a glass substrate from a portion of the edge area; and a protecting device formed on the groove part, wherein the groove part penetrates the first surface and the second surface.

Abstract: A packaging substrate includes a core layer including a glass substrate with a first surface and a second surface facing each other, and a plurality of core vias. The plurality of core vias penetrating through the glass substrate in a thickness direction, each comprising a circular core via having a circular opening part and a non-circular core via having an aspect ratio of 2 to 25 in the x-y direction of an opening part. One or more electric power transmitting elements are disposed on the non-circular core via.

Abstract: Embodiments relate to a semiconductor packaging substrate, a semiconductor packages, and a method for manufacturing the semiconductor packaging substrate, wherein a substrate comprising a one surface, other surface facing the one surface, a recessed surface that the one surface recessed, and a side wall connecting the one surface and the recessed surface; and plurality of first vias that penetrating the recessed surface and the other surface; wherein the plurality of first vias include a thermally conductive material. Embodiments have an excellent heat dissipation effect and can prevent warpage on the surface of the substrate due to thermal expansion.

Abstract: A packaging substrate according to an embodiment has an upper surface and a lower surface. The packaging substrate includes a mounting region in which an element is accommodated and a core substrate in which the mounting region is disposed. The mounting region includes a cavity portion formed by recessing a portion of the core substrate, a cavity portion side surface formed inside the core substrate in a thickness direction of the core substrate to form an outer periphery of the cavity portion, and a first heat dissipation portion disposed adjacent to the outer periphery of the cavity portion. The first heat dissipation portion is a thermal path through which heat of the packaging substrate is transmitted to the outside. The first heat dissipation portion includes one or more heat dissipation vias each having an area of 5,000 ?m2 to 75 mm2 when viewed from the upper surface of the packaging substrate.

Abstract: A packaging substrate according to an embodiment includes a cavity region in which an element is accommodated, and a core substrate in which the cavity region is disposed. The cavity region includes an accommodation portion that is a space formed by recessing a portion of the core substrate, a side surface that is formed on an inner side in a thickness direction of the core substrate and forms an outer periphery of the accommodation portion, and an elastic layer disposed adjacent to the side surface. An elastic modulus of the elastic layer is 2 GPa to 15 GPa. The packaging substrate may have excellent thermomechanical reliability and long-term durability.

Abstract: An embodiment relates to a substrate and a semiconductor module. A substrate capable of manufacturing a substrate for packaging, which is an individual product, with excellent yield despite cracks that may occur at edges or side surfaces of a core is provided.

Abstract: An embodiment relates to a loading cassette and a target substrate loading method to which same is applied. The loading cassette according to the embodiment comprises: an upper plate; a lower plate facing the upper plate while having a space therebetween; an edge support part for connecting the upper plate to the lower plate and supporting the left and right edges of a target substrate; and a rear surface support part for connecting the upper plate to the lower plate and supporting the center and the rear surface-edge of the target substrate.

Abstract: The embodiment relates to a packaging substrate and a semiconductor device, including an element unit including a semiconductor element; and a packaging substrate electrically connected to the element unit; and it applies a glass substrate as a core of the packaging substrate, thereby can significantly improve electrical properties such as a signal transmission rate by connecting the semiconductor element and a motherboard to be closer to each other so that electrical signals are transmitted through as short a path as possible. Therefore, it can significantly improve electrical properties such a signal transmission rate, substantially prevent generating of parasitic element, and simplify a process of treatment for an insulating layer, and thus provides a packaging substrate applicable to a high-speed circuit.

Abstract: The embodiment relates to a packaging substrate and a semiconductor apparatus, including an element unit including a semiconductor element; and a packaging substrate electrically connected to the element unit; and it applies a glass substrate as a core of the packaging substrate, thereby can significantly improve electrical properties such as a signal transmission rate by connecting the semiconductor element and a motherboard to be closer to each other so that electrical signals are transmitted through as short a path as possible. Therefore, it can significantly improve electrical properties such a signal transmission rate, substantially prevent generating of parasitic element, and simplify a process of treatment for an insulating layer, and thus provides a packaging substrate applicable to a high-speed circuit.

Abstract: A packaging substrate is provided. The packaging substrate includes a first area without a cavity and a second area with a cavity. The first area has first and second surfaces facing each other, and a cavity structure of the second area includes a cavity space; a contact surface; and a side wall. The contact surface is disposed opposite to the opening of the cavity structure. A value of a surface roughness of the contact surface is approximately three times or less of a value of a surface roughness of the first surface of the first area.

Abstract: The present disclosure relates to a core-substrate, a substrate, a use of the substrate, and a semiconductor device comprising the same, wherein the core-substrate is a core-substrate applied to the manufacture of a semiconductor packaging substrate, and the core-substrate distinguished into a product area where a product utilized as a substrate of an individual semiconductor is disposed; and a blank area excepting for the product area, wherein the blank area comprises a protective area disposed between the product area and the substrate, and the protective area comprises a concave or a via. The embodiment can substantially suppress the occurrence of damage in the product area utilized as a substrate for semiconductor packaging, even though a core-substrate which may be easily broken by external impact.

Abstract: A connection structure of vias is provided. The connection structure includes multiple vias which are disposed within an insulting layer to connect electrical signals in upward and downward directions, the multiple vias comprise a first via and a second via disposed in a vertically stacked relationship with each other, the first via and the second via are configured to meet at a same surface, and the second via and the first via are disposed in respectively different numbers.

Abstract: An electronic element packaging substrate and manufacturing method are provided. The substrate includes finer wire widths, transmits signals with low resistance, and provides a compact electronic element package. The substrate may be driven with high efficiency even when high frequency power is applied thereto.

Abstract: A substrate carrier and a substrate assembly comprising the same are provided. The substrate carrier comprises an accommodation space; a guide unit disposed adjacent to the accommodation space; and a supporting unit disposed under the accommodation space and the guide unit. The guide unit comprises a circular shape or an arc shape in the circumference when viewed from an upper position.

Abstract: A manufacturing method for a cleaned packaging substrate is provided. The method is applied to a manufacturing process for a glass substrate or a packaging substrate comprising the same, and comprises a preparing process of disposing a target substrate inside a chamber; and a removing process of jetting ionized air on at least one surface of the target substrate to separate particle impurities, and manufacturing a cleaned packaging substrate. The target substrate is a glass packaging substrate, or a packaging substrate, and the packaging substrate comprises the glass packaging substrate and a redistribution layer disposed on at least one surface of the glass packaging substrate.

Abstract: Disclosed are a packaging substrate comprising a glass substrate comprising a first surface and a second surface which is the opposite surface of the first surface; a cavity unit forming a space inside the glass substrate; a cavity frame dividing the space into plural districts; and a cavity element comprised in at least some of the cavity unit, wherein the cavity frame comprises plural frame through holes penetrating in a direction from the one side to the other side.

Abstract: A packaging substrate includes a core layer including a glass substrate with a first surface and a second surface facing each other, and a plurality of core vias. The plurality of core vias penetrating through the glass substrate in a thickness direction, each comprising a circular core via having a circular opening part and a non-circular core via having an aspect ratio of 2 to 25 in the x-y direction of an opening part. One or more electric power transmitting elements are disposed on the non-circular core via.

Abstract: The embodiment relates to a packaging substrate and a semiconductor device, comprising an element unit comprising a semiconductor element; and a packaging substrate electrically connected to the element unit; and it applies a glass substrate as a core of the packaging substrate, thereby can significantly improve electrical properties such as a signal transmission rate by connecting the semiconductor element and a motherboard to be closer to each other so that electrical signals are transmitted through as short a path as possible. Therefore, it can significantly improve electrical properties such a signal transmission rate, substantially prevent generating of parasitic element, and simplify a process of treatment for an insulating layer, and thus provides a packaging substrate applicable to a high-speed circuit.

Abstract: A packaging substrate and a semiconductor device comprising a semiconductor element, include a core layer and an upper layer disposed on the core layer, and the core layer includes a glass substrate as a core of the packaging substrate to improve electrical properties such as a signal transmission rate by connecting the semiconductor element and a mother board to be closer to each other so that electrical signals are transmitted through as short a path as possible.