Abstract: A method for identifying a bus memory region in a dynamic manner that is cost effective and suitable for plug-and-play systems is provided. The method includes the steps of a) identifying first signals that initiate a bus cycle, the first signals specifying a first address in the memory region; b) storing the first address as a reference address for the memory region; c) receiving second signals specifying an operation and a second address; d) comparing the second address with the reference address; and e) proceeding with the operation on the bus if the comparing step confirms the second address references the memory region. A device according to the present invention may include a bus-cycle discriminator, a latch, a comparing device, and a controller which allows the bus memory region to be identified without any change to the hardware even when the memory segments of the relevant bus changes.