Patents Assigned to Acatel
  • Publication number: 20150084182
    Abstract: Various embodiments relate to a microchip die cooling assembly comprising a circuit board; a microchip having an exposed die attached to the circuit board; a heatspreader having a top side and a bottom side; a heat sink having a bottom side and a top side comprising a cooling structure; a first thermal interface material in contact with the exposed die and the bottom side of the heatspreader; and a second thermal interface material in contact with the top side of the heat spreader and the bottom side of the heat sink.
    Type: Application
    Filed: September 26, 2013
    Publication date: March 26, 2015
    Applicant: ACATEL LUCENT CANADA, INC.
    Inventors: STEFANO F. DE CECCO, GREGORY W. CHESHIRE
  • Patent number: 7525917
    Abstract: A traffic control system and method with flow control aggregation. The system includes a switching fabric and an ingress module. The switching fabric includes read counters that are associated with a plurality of queues. The read counters represent an aggregated number of cells dequeued from respective queues since a previous flow control message (FCM) was sent to the ingress module. The read counters are reset when a FCM is created. The ingress module includes write counters that are associated with the queues. The write counters are incremented each time a cell is sent to the respective queues. The write counters are decremented in accordance with the FCM when the FCM is received. Also, read counters for one or more queues are aggregated into a single FCM.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: April 28, 2009
    Assignee: Acatel-Lucent USA Inc.
    Inventors: Philip Ferolito, Eric Anderson, Gregory S. Mathews
  • Publication number: 20080049923
    Abstract: A Communication system comprising at least a Private Branch Exchange and a computer with Computer to Telephone Integration server, the Private Branch Exchange and the Computer to Telephone Integration server based on Computer Supported telephony Application Standard, wherein the private branch exchange as well as the Computer to Telephone Integration server comprise means to exchange SMS with each other
    Type: Application
    Filed: December 6, 2005
    Publication date: February 28, 2008
    Applicant: Acatel Lucent
    Inventor: Raymond Gass
  • Patent number: 7324446
    Abstract: The present invention relates to a communication method, and related buffering and line termination elements to be used in a communication network. The communication network includes a buffering element, a line termination element and several network termination elements. The buffering element is coupled to the line termination element, and the line termination element is coupled to each of the network termination elements over a shared medium. The buffering element and the line termination element interact in such a way that the line termination element adjusts a cell input/output rate of the buffering element to bandwidth related conditions of the network termination elements, or vice versa.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: January 29, 2008
    Assignee: Acatel
    Inventors: Kristiaan Johan Hubert Ghislanus Venken, Stefaan Jozef De Cnodder
  • Patent number: 6268743
    Abstract: An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of a B16×16 tile, and also associated with each of the I/O blocks is a freeway routing channel. A B16×16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. At the lowest level of the semi-hierarchical FPGA architecture, there are block connect (BC) routing channels, local mesh (LM) routing channels, and direct connect (DC) interconnect conductors to connect the logic elements to further routing resources. Each B1 block includes four clusters of devices. Each of the four clusters includes first and second LUT3s, a LUT2, and a DFF .
    Type: Grant
    Filed: March 6, 2000
    Date of Patent: July 31, 2001
    Assignee: Acatel Corporation
    Inventor: Sinan Kaptanoglu
  • Patent number: 4736513
    Abstract: A miniature variable inductor comprises a coil soldered to a pair of connecting skids. These skids are clipped to two oppositely disposed lateral walls of an injection-molded plastics cover in the shape of a hollow die. A solid part of the cover and a hollow space lie between these two walls. A central opening through these walls, the solid part of the cover and the hollow space defines a housing for a movable ferromagnetic core. There is a screwthread on at least part of this core. The coil is disposed in the aforementioned hollow space coaxially with the central opening, encapsulated in resin. The central opening has a threaded portion where it passes through the solid part of the cover. This threaded portion is complementary to the thread on the core.
    Type: Grant
    Filed: August 24, 1987
    Date of Patent: April 12, 1988
    Assignee: Acatel
    Inventors: Guy Barbier, Jean-Paul Amory