Patents Assigned to Acco Semiconductor, Inc.
  • Patent number: 8928410
    Abstract: Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: January 6, 2015
    Assignee: ACCO Semiconductor, Inc.
    Inventors: Alexandre G. Bracale, Denis A. Masliah
  • Patent number: 8731485
    Abstract: RF switching devices are provided that alternatively couple an antenna to either a transmitter amplifier or a receiver amplifier. An exemplary RF switching device comprises two valves, one for a receiver transmission line between the antenna and the receiver amplifier, the other for a transmitter transmission line between the antenna and the power amplifier. Each valve is switchably coupled between ground and its transmission line. When coupled to ground, current flowing through the valve increases the impedance of the transmission line thereby attenuating signals on the transmission line. When decoupled from ground, the impedance of the transmission line is essentially unaffected. The pair of valves is controlled such that when one valve is on the other valve is off, and vice versa, so that the antenna is either receiving signals from the power amplifier or the receiver amplifier is receiving signals from the antenna.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: May 20, 2014
    Assignee: Acco Semiconductor, Inc.
    Inventor: Denis A. Masliah
  • Publication number: 20130303093
    Abstract: RF switching devices are provided that alternatively couple an antenna to either a transmitter amplifier or a receiver amplifier. An exemplary RF switching device comprises two valves, one for a receiver transmission line between the antenna and the receiver amplifier, the other for a transmitter transmission line between the antenna and the power amplifier. Each valve is switchably coupled between ground and its transmission line. When coupled to ground, current flowing through the valve increases the impedance of the transmission line thereby attenuating signals on the transmission line. When decoupled from ground, the impedance of the transmission line is essentially unaffected. The pair of valves is controlled such that when one valve is on the other valve is off, and vice versa, so that the antenna is either receiving signals from the power amplifier or the receiver amplifier is receiving signals from the antenna.
    Type: Application
    Filed: July 19, 2013
    Publication date: November 14, 2013
    Applicant: ACCO Semiconductor, Inc.
    Inventor: Denis A. Masliah
  • Patent number: 8532584
    Abstract: RF switching devices are provided that alternatively couple an antenna to either a transmitter amplifier or a receiver amplifier. An exemplary RF switching device comprises two valves, one for a receiver transmission line between the antenna and the receiver amplifier, the other for a transmitter transmission line between the antenna and the power amplifier. Each valve is switchably coupled between ground and its transmission line. When coupled to ground, current flowing through the valve increases the impedance of the transmission line thereby attenuating signals on the transmission line. When decoupled from ground, the impedance of the transmission line is essentially unaffected. The pair of valves is controlled such that when one valve is on the other valve is off, and vice versa, so that the antenna is either receiving signals from the power amplifier or the receiver amplifier is receiving signals from the antenna.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: September 10, 2013
    Assignee: ACCO Semiconductor, Inc.
    Inventor: Denis A. Masliah
  • Patent number: 8400222
    Abstract: Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: March 19, 2013
    Assignee: ACCO Semiconductor, Inc.
    Inventors: Alexandre G. Bracale, Denis A. Masliah
  • Patent number: 8334178
    Abstract: A double-gate semiconductor device includes a MOS gate and a junction gate, in which the bias of the junction gate is a function of the gate voltage of the MOS gate. The breakdown voltage of the double-gate semiconductor device is the sum of the breakdown voltages of the MOS gate and the junction gate. The double-gate semiconductor device provides improved RF capability in addition to operability at higher power levels as compared to conventional transistor devices. The double-gate semiconductor device may also be fabricated in a higher spatial density configuration such that a common implantation between the MOS gate and the junction gate is eliminated.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: December 18, 2012
    Assignee: ACCO Semiconductor, Inc.
    Inventors: Denis A. Masliah, Alexandre G. Bracale, Francis C. Huin, Patrice J. Barroul
  • Patent number: 8188540
    Abstract: A double-gate semiconductor device includes a MOS gate and a junction gate, in which the bias of the junction gate is a function of the gate voltage of the MOS gate. The breakdown voltage of the double-gate semiconductor device is the sum of the breakdown voltages of the MOS gate and the junction gate. The double-gate semiconductor device provides improved RF capability in addition to operability at higher power levels as compared to conventional transistor devices. The double-gate semiconductor device may also be fabricated in a higher spatial density configuration such that a common implantation between the MOS gate and the junction gate is eliminated.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: May 29, 2012
    Assignee: ACCO Semiconductor, Inc.
    Inventors: Denis A. Masliah, Alexandre G. Bracale, Francis C. Huin, Patrice J. Barroul
  • Patent number: 8179197
    Abstract: Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: May 15, 2012
    Assignee: ACCO Semiconductor, Inc.
    Inventors: Alexandre G. Bracale, Denis A. Masliah
  • Patent number: 8159298
    Abstract: Linearization circuits of the invention are used in conjunction with power amplification circuits that comprise a power amplifier core. Exemplary linearization circuits comprise a replica of the power amplifier core. In operation, the linearization produces an envelope signal from an RF signal. The envelope signal is used to control the replica to produce an analog output signal which represents the inverse of the AM to AM distortion of the power amplifier core. The linearization circuit then biases the RF signal with the inverted non-linear signal of the replica to control the power amplifier core. The power amplifier core and the replica thereof can be defined on the same semiconductor die so both respond to process variables similarly.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: April 17, 2012
    Assignee: ACCO Semiconductor, Inc.
    Inventors: Sylvain Quack, Angelo Malvasi
  • Patent number: 7969243
    Abstract: Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: June 28, 2011
    Assignee: Acco Semiconductor, Inc.
    Inventors: Alexandre G. Bracale, Denis A. Masliah
  • Patent number: 7969341
    Abstract: A multi-stage sigma-delta modulator including bit truncation between stages. The bit truncation reduces the number of bits that must be processed in subsequent stages and thus allows for faster response times. In some embodiments, the gain of a feedback loop is selected to compensate for the bit truncation such that the sigma-delta modulator operates in a stable state.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: June 28, 2011
    Assignee: Acco Semiconductor, Inc.
    Inventors: Michel Robbe, Stephan Doucet
  • Patent number: 7952431
    Abstract: Linearization circuits of the invention are used in conjunction with power amplification circuits that comprise a power amplifier core. Exemplary linearization circuits comprise a replica of the power amplifier core. In operation, the linearization produces an envelope signal from an RF signal. The envelope signal is used to control the replica to produce an analog output signal which represents the inverse of the AM to AM distortion of the power amplifier core. The linearization circuit then biases the RF signal with the inverted non-linear signal of the replica to control the power amplifier core. The power amplifier core and the replica thereof can be defined on the same semiconductor die so both respond to process variables similarly.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: May 31, 2011
    Assignee: ACCO Semiconductor, Inc.
    Inventors: Sylvain Quack, Angelo Malvasi
  • Patent number: 7863645
    Abstract: A double-gate semiconductor device provides a high breakdown voltage allowing for a large excursion of the output voltage that is useful for power applications. The double-gate semiconductor device may be considered a double-gate device including a MOS gate and a junction gate, in which the bias of the junction gate may be a function of the gate voltage of the MOS gate. The breakdown voltage of the double-gate semiconductor device is the sum of the breakdown voltages of the MOS gate and the junction gate. Because an individual junction gate has an intrinsically high breakdown voltage, the breakdown voltage of the double-gate semiconductor device is greater than the breakdown voltage of an individual MOS gate. The double-gate semiconductor device provides improved RF capability in addition to operability at higher power levels as compared to conventional transistor devices.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: January 4, 2011
    Assignee: ACCO Semiconductor Inc.
    Inventors: Denis A. Masliah, Alexandre G. Bracale, Francis C. Huin, Patrice J. Barroul
  • Patent number: 7808415
    Abstract: A multi-stage sigma-delta modulator including bit truncation between stages. The bit truncation reduces the number of bits that must be processed in subsequent stages and thus allows for faster response times. In some embodiments the gain of a feedback loop is selected to compensate for the bit truncation such that the sigma-delta modulator operates in a stable state.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: October 5, 2010
    Assignee: Acco Semiconductor, Inc.
    Inventors: Michel Robbe, Stephan Doucet