Abstract: An XOR circuit, a RAID device which can recover several failures and method thereof are provided. A Galois field data recovery circuit having two or more sets of Galois Field engine circuits which are used in the XOR circuit, is one which can generate high efficient parity engine and high efficient flow data route and which at the same time correct the three or more failures during operation of the RAID device.

Abstract: A method of creating a multiple of virtual Serial Advanced Technology Attachment ports in a disk array controller, and the method builds a port multiplier in a Serial Advanced Technology Attachment disk array controller by a software method, and the port multiplier defines several slices capable of identifying the address of a computer host system. The port multiplier is connected to at least one disk set, and each disk is divided into several data blocks corresponding to data blocks of another disk of the same disk set to constitute a synchronously updated disk backup system. The software method provides a method of connecting several storage units to overcome the restriction on the point-to-point connection of the Serial Advanced Technology Attachment disk array system, so as to achieve a multi-driving function and a serial bus system.

Abstract: An XOR circuit, a RAID device which can recover several failures and method thereof are provided. A Galois field data recovery circuit having two or more sets of Galois Field engine circuits which are used in the XOR circuit, is one which can generate high efficient parity engine and high efficient flow data route and which at the same time correct the three or more failures during operation of the RAID device.

Abstract: An XOR circuit, a RAID device which can recover several failures and method thereof are provided. A Galois field data recovery circuit having two or more sets of Galois Field engine circuits which are used in the XOR circuit, is one which can generate high efficient parity engine and high efficient flow data route and which at the same time correct the three or more failures during operation of the RAID device.

Abstract: A disk controller, and more particularly, a redundant arrays of inexpensive disks (RAID) controller, is disclosed. The RAID controller includes: a redundant arrays of inexpensive disks (RAID) controller board, a memory module slot mounted on the controller board for inserting therein a 144-pin small outline dual inline memory module (SODIMM), an I/O processor mounted on the controller board and electrically connected with the memory module slot for transmitting a data clock signal and an error-prevention data, and a random access memory integrated chip (RAM IC) mounted on the controller board and electrically connected with the I/O processor for storing the error-prevention data.

Abstract: A disk array controller is configured to communicate with the PCI-based host computer with a known standard PCI protocol. The standard PCI protocol typically defines a message provided for the disk array controller to negotiate with the PCI-based host computer. The message is represented by the PCI class code. By programming the PCI class code register in the PCI configuration space register (offset address 09H-0BH) with appropriate hex codes, the disk array controller will be identified as a stand PCI bus master IDE controller, and can be driven by the PCI bus master IDE controller driver utility, which is built in most of the PC-based operating system.