Abstract: In the preferred embodiment for forming a ragged polysilicon crown-shaped capacitor of a memory cell, a first dielectric layer is formed on a semiconductor substrate. A portion of the first dielectric layer is removed to define a contact hole within the first dielectric layer, wherein the contact hole is extended down to a source region in the substrate. Next, a conductive plug is formed and is communicated to the source region within the contact hole. A second dielectric layer is formed on the first dielectric layer and the conductive plug, and a third dielectric layer is formed on the second dielectric layer. Next, portions of the third dielectric layer and the second dielectric layer are removed to define a storage node opening, wherein the storage node opening is located over the conductive plug. A first conductive layer is then formed to conformably cover the inside surface of the storage node opening and on the third dielectric layer.

Abstract: The method of the present invention is to fabricate a CMOS device without boron penetration. A nitrided gate oxide and SAS gate electrode are provided to suppress boron penetration. The nitrided gate oxide could be formed in two approaches. One of the approaches is to implant nitrogen ions into the interface between substrate and pad oxide layer, and then thermally treat the substrate for segregating the doped nitrogen ions in the surface of substrate. Removing the pad oxide layer, thermally treating the substrate in oxygen ambient for growing a gate oxide layer, the nitrided gate oxide layer is formed by incorporating doped nitrogen ions into the growing gate oxide layer. The other approach is to place the substrate having a gate oxide layer thereon in nitrogen plasma ambient, thereby forming the nitrided gate oxide layer. After the formation of nitrided gate oxide layer, at least one stacked amorphous silicon (SAS) layer is formed over the gate oxide layer.

Abstract: A method of simulating a post-exposure bake (PEB) process for chemically amplified resists having photoacids and protection-sites comprises the following steps. First, the initial PEB parameters are input to represent a temperature-time history of the PEB process. Then, the reaction constants and a diffusion coefficient are input to represent the chemically amplified resists. Wherein the reaction constants are temperature-dependent, and the diffusion coefficient is temperature-dependent and protection-site-dependent in the entire course of the PEB simulation. The protection-site concentration of the chemically amplified resists is computed by using an implicit scheme, and the photoacid concentrations are computed in a space occupied by the chemically amplified resists based on the diffusion coefficient by using an implicit scheme.

Abstract: In the preferred embodiment for forming a ragged polysilicon crown-shaped capacitor of a memory cell, a first dielectric layer is formed on a semiconductor substrate. A portion of the first dielectric layer is removed to define a contact hole within the first dielectric layer, wherein the contact hole is extended down to a source region in the substrate. Next, a conductive plug is formed and communicated to the source region within the contact hole. A second dielectric layer is formed on the first dielectric layer and the conductive plug, and a third dielectric layer is formed on the second dielectric layer. Next, portions of the third dielectric layer and the second dielectric layer are removed to define a storage node opening, wherein the storage node opening is located over the conductive plug. A first conductive layer is then formed to conformably cover the inside surface of the storage node opening and on the third dielectric layer.

Abstract: In the preferred embodiment for forming a ragged polysilicon crown-shaped capacitor of a dynamic random access memory cell, a first dielectric layer is formed on a semiconductor substrate. A portion of the first dielectric layer is removed to define a contact hole within the first dielectric layer, wherein the contact hole is extended down to a source region in the substrate. Next, a conductive plug is formed and communicated to the source region within the contact hole. A second dielectric layer is formed on the first dielectric layer and the conductive plug, and a third dielectric layer is formed on the second dielectric layer. Next, portions of the third dielectric layer and the second dielectric layer are removed to define a storage node opening, wherein the storage node opening is located over the conductive plug. A first conductive layer is then formed to conformably cover the inside surface of the storage node opening and on the third dielectric layer.

Abstract: The present invention proposes a method for fabricating high-density and high-speed NAND-type mask read-only memories. This method constructs the doped sources and drains by dopant diffusion into the silicon substrate to form ultra-shallow junction, and therefore minimizes the punch-through issue. First, a stacked thin oxide, doped silicon and silicon nitride layer is deposited on the semiconductor substrate and then bit line regions is defined. Gate oxide film is formed between the bit line regions and the dopants in the silicon layer are driven into the substrate to form shallow junctions for source and drain regions. A doped polysilicon layer is deposited on the substrate and a chemical mechanical polishing process is carried out with the silicon nitride as the stopping layer. A coding implantation is performed and a conductive layer is defined on the polysilicon layer to be the word lines.

Abstract: A method for forming mask read-only memories comprises: A gate oxide layer is formed on a semiconductor substrate. A polysilicon layer is formed on the gate oxide layer. Then, a silicon nitride layer is formed on said polysilicon layer. The gate structures are defined by patterning the silicon nitride layer and the polysilicon layer. Subsequently, the silicon oxide spacers are formed on the sidewalls of the gate structures. An ion implantation is performed to form the buried bit lines in said semiconductor substrate between said gate structures. A BPSG layer is formed on said semiconductor substrate. Then, the BPSG layer is polished until the top surface of said gate structures and the silicon nitride layer is removed. A conductive layer is formed along the surfaces of said residual BPSG layer, silicon oxide spacers and polysilicon layer.

Abstract: The present invention is a method of fabricating void-free and volcano-free tungsten plugs. A silicon film was formed over contact hole surfaces for restricting the reflow of a dielectric layer. A titanium film is formed over the silicon layer. By performing a thermal process to the silicon layer and the titanium layer in a nitride-containing environment, the etching damage to the substrate can be recovered and a silicon silicide and a titanium nitride can be formed. The contact resistance of plugs can be significantly reduced, when compared with known technology. The undesired formation of voids and volcano can be eliminated. The method can be employed to fabricate defect-free advanced ULSI devices.

Abstract: The structure of flash EEPROM is formed on a composite substrate, wherein said composite substrate comprises: a pad oxide layer formed on a semiconductor substrate; an n-type doped dielectric layer is formed on the pad oxide layer. A nitride layer is formed on the n-type doped oxide layer. The composite substrate has a trench. An oxynitride layer which serves as coupling oxide layer is formed on surfaces of sidewalls and bottom of portion of the semiconductor substrate of the trench. The trench is filled with an n-type conductive doped polysilicon layer. The n-type conductive doped polysilicon layer serves as a floating gate of EEPROM. A conductive layer, a semiconductor substrate layer doped by using aforementioned n-type dopant containing oxide as a diffusion source, serves as buried bit lines being formed in the semiconductor substrate and abutting the pad oxide layer. An ONO layer is formed on the polysilicon layer and the nitride layer.

Abstract: The present invention discloses an isolation method for fabricating isolation regions with less bird's peak sizes in semiconductor devices. A first pad oxide layer and a silicon nitride layer are first formed on a wafer substrate. After an undercut process is performed to the first pad oxide layer and forms a cave under the silicon nitride layer, a second pad oxide layer is formed over the wafer substrate. Next, a polysilicon layer is then deposited along the profile described above. Then, an anisotropic process is used to form sidewall spacers by etching the polysilicon layer. A recessed structure is then formed to the wafer substrate by a semi-isotropic process, and follows a thermal oxidation to fabricate isolation regions composed of silicon dioxide on the surface of the wafer substrate. The silicon nitride layer and the first pad oxide layer are then removed for continuing the active region processes.

Abstract: The present invention provides a gas vent system for a vacuum chamber. The particle placed onto the wafer after loading out from a vacuum chamber can be greatly reduced by the system design. The gas vent system has a gas supply, an anti-vibrating tube, a gas regulator, a first line, a second line, a vent valve, and a filter. The anti-vibrating tube is connected after the gas supply for transferring gas without introducing vibration. The gas regulator is connected after the anti-vibrating tube for controlling a flow rate of the gas. The first line is connected after the gas regulator and has a first metering valve. The second line is connected after the gas regulator and is also connected in parallel with the first line. The second line has a second metering valve and an in-line valve in series. The vent valve is connected after the first line and the second line. The filter is connected between the vent valve and the vacuum chamber.

Abstract: The present invention proposes a method for fabricating field oxide regions for isolation by an improved poly-buffered local oxidation of silicon (PBLOCOS) process. A polysilicon layer is utilized to reduce the bird's beak, and a thin thermal oxide film is formed on the buffered polysilicon film to prevent pitting formation. Forming a thin pad oxide and a silicon layer, a thermal oxidation is carried out to grow another pad oxide on the silicon layer and crystallize the silicon into polysilicon. The buffered layer of stacked oxide-polysilicon-oxide layer is thus formed. The silicon nitride layer is then deposited on the stacked buffered layer and the active areas are defined. A thermal oxidation is now performed, and thick field oxide regions are grown. After the masking nitride layer and the stacked buffered layer are stripped, the MOS devices are fabricated, and thus complete the present invention.

Abstract: The mask ROM cell structure is described as follows: a plurality of first polysilicon gates is formed on the semiconductor substrate, being separated to keep a space. Each of first polysilicon gates comprises first nitride layer/ a n+ polysilicon layer/a first pad oxide layer, and two spacers that formed over the remnant portion of the pad oxide layer, and formed, respectively, on two sidewalls of the first nitride layer 130, and the first n+ polysilicon layer. A plurality of second polysilicon gates is formed on the semiconductor substrate 105. Each of the second polysilicon gates comprises second n+doped polysilicon gate/second pad oxide layer, wherein the pad oxide layer is formed on the semiconductor substrate, and the n+doped polysilicon gate is formed on the second pad oxide layer. The first polysilicon gates separate the second polysilicon gates each.

Abstract: In the preferred embodiment for forming a rugged polysilicon cup-shaped capacitor of a dynamic random access memory cell, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed on the first dielectric layer, followed by the formation of a first conductive layer on the second dielectric layer. Portions of the first conductive layer and the second dielectric layer are then removed to define an opening therein. A second conductive layer is formed conformably on the substrate within the opening and on the first conductive layer. A sidewall structure is then formed within the opening on sidewalls of the second conductive layer. Next, a removing step is performed to remove a portion of the second conductive layer which is uncovered by the sidewall structure. The sidewall structure and a portion of the first dielectric layer are removed, using the residual second conductive layer as a mask, to define a contact hole within the first dielectric layer.

Abstract: The capacitor of the present invention mainly includes the storage node 52, the capacitor dielectric layer 54, and the conductive layer 56. The storage node 52 is formed on the semiconductor substrate 30, and the storage node 52 includes a base member 52a, two vertical members 52b, two horizontal members 52c, and two sidewall members 52d, in which the base member 52a provides a conductive communication to an underlying conductive region in the substrate 30, the two vertical members 52b respectively extends upward from two lateral ends of the base member 52a, the two horizontal members 52c respectively and outwardly extends from two top ends of the two vertical members 52b, and the two sidewall members 52d respectively and upwardly extending from two outward ends of said two horizontal members 52c. The dielectric layer 54 is covered on the storage node 52 and the conductive layer 56 is formed on the dielectric layer 54.

Abstract: The method of the present invention for forming a capacitor on a semiconductor substrate includes the following steps. At first, a first oxide layer is formed over the substrate and a nitride layer is then formed over the oxide layer. A second oxide layer is formed over the nitride layer and a first silicon layer is formed over the second oxide layer. Next, a node opening is defined in the first silicon layer, the second oxide layer, and the nitride layer, upon the first oxide layer. Sidewall structures are then formed on sidewalls of the node opening. A contact opening is then defined in the first oxide layer under the node opening. The contact opening is defined in the first oxide layer under a region uncovered by the sidewall structures. The sidewall structures and a portion of the nitride layer nearby the node opening are removed to form undercut structures under the second oxide layer.

Abstract: A high-density flat cell mask ROM is disclosed. The mask ROM comprises: a semiconductor substrate having a plurality of trenches and each of the trenches is separated to keep a space with each other. A plurality of oxynitride layers is formed on all sidewall and bottom surfaces of those trenches. A plurality of n+-doped polysilicon layers is formed on the oxynitride layers. A n+ doped silicon layer serves as buried bit line formed in the semiconductor substrate and surrounding the trenches. Each of the doped silicon layers is spaced from the n+-doped polysilicon layers by the oxynitride layer. A plurality of thick oxide layers is formed on the n+ polysilicon layers. A plurality of thin oxide layers are formed on the semiconductor substrate and between those thick oxide layer, and each of thin oxide layers is contiguous with the thick oxide layers.

Abstract: This invention discloses a novel design to fabricate a ring-like capacitor in a semiconductor memory device for increasing the area of the capacitor electrodes. The ring-like conductive structure of the electrode of the capacitor includes a mushroom-shaped member having a flat-headed cap and a stem coupled to the source region of the semiconductor memory device, a solid cylindrical member disposed on the cap of the mushroom-shaped member, and a side-wall spacer being a hollow cylindrical member disposed on the cap of said mushroom-shaped member to increase the area of the capacitor electrodes thereby increasing the capacitance of the capacitor to provide a sufficient capacitance while maintaining high integration in semiconductor memory cells.

Abstract: The present invention is a method of manufacturing a high density capacitor for use in semiconductor memories. High etching selectivity between BPSG (borophosphosilicate glass) and CVD-oxide (chemical vapor deposition oxide) is used to fabricate a capacitor with a plurality of horizontal fins. First, a nitride layer is formed on a semiconductor substrate. A stacked layer consists of BPSG and silicon oxide formed on the nitride layer. Then a contact hole is formed in the stacked layer and the nitride layer. A highly selective etching is then used to etch the BPSG sublayers of the stacked layer. Next, a first polysilicon layer is formed in the contact hole and the stacked layer, subsequently, a dielectric layer is formed on the first polysilicon layer. Then, undoped hemispherical-grain silicon (HSG--Si) is formed on the dielectric layer. Next, a portion of the dielectric layer is etched using the HSG--Si layer as a hard mask to expose a portion of the first polysilicon layer.

Abstract: This invention discloses a novel design for increasing the surface area of a stacked capacitor used in DRAM devices. The upper and lower plates of the capacitor comprises of several concave structures. The concave structures are first produces on an LS-SOG layer using focused ion beam lithography, which is then mapped to the lower plate of the capacitor. A dielectric layer is deposited, after which an upper plate is formed. The concave structures increases the plate area, thereby increasing charge storage capacity.