Abstract: The present invention proposes a shallow trench isolation region in a semiconductor substrate for ULSI devices. The trench region includes a thermal oxide film formed on the bottom and the sidewall, a CVD dielectric film formed on the bottom of the thermal oxide film, and a channel stop region formed beneath the bottom of the thermal oxide film. The processes described as follows. Forming a pad oxide/silicon nitride layer on the substrate, the trench region and active area are defined. After silicon spacers are formed, the silicon substrate is recessed to form trench region by using the silicon nitride layer and silicon spacers as etching mask. A channel stopping implantation is performed. Then a thermal oxide film is regrown on the trench surface. After removing the silicon nitride layer, a thick CVD dielectric layer is deposited on the substrate. The dielectric film outside the trench region is removed by a CMP process, and thus the present invention complete.