Abstract: Interleaved Analogue to Digital converter, comprising a plurality of individual ADCs (71). A digital filter stage (20) is used for equalizing the responses of the individual ADCs, and comprises a FIR filter in which the coefficient table is cyclically reloaded between ADCs' samples, in order to reduce the number of multipliers required.

Abstract: In a modular data acquisition system (4), a module comprises at least one analog-to-digital converter (12) for converting an analog input signal (IN1, IN2, IN3, IN4) into a digital signal (OUT1, OUT2, OUT3, OUT4), and a clock generating circuit (20) for supplying an internal clock signal (209). The module further comprises a connector for plugging in a removable connecting element (3) on the front side of the module (1) in order to connect it to a synchronization bus connecting several modules in said system. A clock selecting circuit (204) enables the selection of either a slave-clock status, wherein the converters (12) are synchronized by an external synchronization signal supplied by said synchronization bus, or of a master-clock status, wherein the converters are synchronized by said internal clock signal which is also used a external synchronization signal on said synchronization bus. Trigger signals can also be transmitted by the synchronization bus and by the connecting elements.

Abstract: Interleaved Analogue to Digital converter, comprising a plurality of individual ADCs (71). A digital filter stage (20) is used for equalizing the responses of the individual ADCs, and comprises a FIR filter in which the coefficient table is cyclically reloaded between ADCs' samples, in order to reduce the number of multipliers required.

Abstract: The analog-to-digital conversion circuit for high-frequency data acquisition system comprises a plurality of digitizers (6, 9) capable of sampling and digitizing a high-frequency analog input signal (a; w1), the sampling times of the different digitizers being phase-shifted, and a circuit (3, 4, 5, 8, 11) for calibrating the phase shift between a first digitizer and a second digitizer. The phase shift calibration circuit (3, 4, 5, 8, 11) determines a phase shift correction value (u) so as to minimize the difference between a sequence of digital values (ri) determined by the first digitizer (6) and a sequence of corresponding digital values (ui) determined by interpolating the digital values (si) supplied by the second digitizer (9).

Abstract: A data acquisition module (1) includes an interconnection board (15) with several electronic components (3, 18) mounted on at least one side of said board. A protective cover (16) mounted opposite said side covers the electronic components (3, 18). In order to cool notably the module's analog-to-digital converters, a piston 41 connected to the protective cover (16) is pressed by a spring (43) against the upper side of at least one electronic component (3) so as to establish a thermal bridge between said electronic component and said protective cover. The piston is mounted in a piston carrier fastened on the cover (16). The diameter of the portion (410) of the piston (41) that is in contact with the electronic component (3) to be cooled is smaller than the diameter of the portion (411) of the piston that is in contact with the piston carrier (40).

Abstract: The circuit for converting a high-frequency analog input signal (a) into a plurality of digital signals (D1-DN) for processing by a digital processor (8) in a data acquisition system comprises: an analog-to-digital m-bits converter (1), a memory (5) for storing the digital data (d1-dN) converted by said converter, said memory being accessible by said digital processor (8), a circuit (6) for analyzing in real time said digital data (D1-DN), capable of modifying the storage address of said digital data (D1-DN) in said memory (5) following the detection of a predefined event in said digital data (D1-DN).