Abstract: A sampling synchronous envelope detector adopts a specialized sample-and-hold ("S&H") approach, basing a detected output on instantaneous values of the carrier waveform which are sampled at specially chosen instants. Non-linear distortion is avoided by timing the sampling instants to occur at or near a carrier wave peak which is subsequent to an earlier carrier wave peak which serves as a time base. Sampling instants occur only at or near positive carrier peaks (or only at or near negative peaks) in a half-wave embodiment, and sampling instants occur at or near both positive and negative carrier peaks in a full wave embodiment. Another aspect of the detector provides means, such as a phase locked loop, for ensuring that the phase of the sampling instants is maintained continuously, even in the event of carrier pinch-off or other event which distorts or minimizes the carrier waveform from which the timing instants would otherwise be determined.

Abstract: The present invention provides a system and method in which an arbitrary information-modulated signal is efficiently amplified to high power levels. The arbitrary information-modulated signal is received at a low power level and is separated into elemental signals. In a preferred embodiment, a frequency/phase information signal and an amplitude information signal are the elemental signals which collectively represent the essential information in the original information-modulated signal. The circuit uses the elemental signals to provide an amplified replica of the original information-modulated signal. The amplification preferably, though not necessarily, involves using the digital amplitude modulators disclosed in U.S. Pat. No. 4,804,931, U.S. Pat. No. 5,260,674, or U.S. Pat. No. 5,367,272.

Abstract: The invention provides various embodiments of a balanced modulator, each of which involves one or more individual amplitude modulators which, individually, do not provide suppressed-carrier outputs. A first embodiment employs a single amplitude modulator whose carrier input is selectively delayed by a half wavelength, depending on the polarity of the input modulating signal, and whose amplitude input receives the absolute value of the modulating input signal. A second embodiment involves summation of the outputs of two amplitude modulators whose carrier inputs are responsive to carrier signals offset by a half carrier wavelength and whose modulating signal inputs are responsive only to signals of respectively opposite polarity. Further, quadrature amplitude modulation (QAM) modulators are provided by a combination of the above-described modulators.

Abstract: A first aspect of the present modulator provides for a reduction in an otherwise maximum level of an analog input signal during a particular time period (for example, the period of the synchronization pulse in an analog television format). When the normally predictable high-amplitude portion is reduced in amplitude, combiner power efficiency is increased. To regain the full amplitude, the gain of the amplifier corresponding to the most significant bit of the digitized signal being modulated, is increased. A second aspect of the present modulator provides an automatic gain control AGC arrangement especially suitable for the modulator of U.S. Pat. No. 4,804,931. The AGC arrangement is based on a circuit that is governed by the output of a respective amplifier as well as by the binary value of the respective bit corresponding to the significance of the amplifier and a reference value related to the bit's significance.

Abstract: The normally slow rise time of a Class C bipolar transistor grounded base RF power amplifier is greatly enhanced by circuitry external to the amplifier transistor. Current is injected into the base of the transistor for the duration of the rise time, biasing it into Class A operation during this period. Then, after the base current injection, operation reverts to Class C to retain amplifier power efficiency. Finally, the normally slow fall time of the bipolar Class C RF power amplifier is greatly enhanced by reverse-biasing the base-to-emitter junction during the fall time. During this fall time the amplifier is forced into its cutoff region by the applied reverse bias, as stored charge is pulled out of the base-emitter region of the transistor. In this manner, the power efficiency advantage of Class C power amplifiers may be retained, while adding the benefits of sharper output rise and fall times that would not otherwise be achieved.

Abstract: A first aspect of the present modulator provides for a reduction in an otherwise maximum level of an analog input signal during a particular time period (for example, the period of the synchronization pulse in an analog television format). When the normally predictable high-amplitude portion is reduced in amplitude, combiner power efficiency is increased. To regain the full amplitude, the gain of the amplifier corresponding to the most significant bit of the digitized signal being modulated, is increased. A second aspect of the present modulator provides an automatic gain control AGC arrangement especially suitable for the modulator of U.S. Pat. No. 4,804,931. The AGC arrangement is based on a circuit that is governed by the output of a respective amplifier as well as by the binary value of the respective bit corresponding to the significance of the amplifier and a reference value related to the bit's significance.

Abstract: A digital amplitude modulator for use in transmitting information signals in the context of AM audio and AM video. The amplitude modulator/transmitter basically consists of a predetermined number of quadrature hybrid power devices configured as combiners and arranged in cascade so that the output of one combiner becomes one of the inputs of its adjacent combiner. An analog signal source such as a microphone or a video generator, produces an analog signal that passes through an analog-to-digital converter. The output of the A/D converter appears on datelines. The data consists of four-bit words. However, it is contemplated that in order to improve the quality of the signals being transmitted, 12- or 16-bit words or any arbitrary n are employed. Each of the bits from the least significant bit (LSB) to the most significant bit (MSB) is fed into a gate. In turn, each of the gates has its output connected to one of the input ports of one of the combiners.