Abstract: A data processor comprises an array of integrated circuits (ICs), each of which comprises an array of data processing elements (PEs) connected to allow transfer of data. The PEs of the data processor may be organized into array-wide rows and columns with data transfer along each row or column. Rows and columns may be subdivided into sections, such division being either intra-chip (all PEs on one IC) or inter-chip (PEs from different ICs), and each section may be arranged for cyclical data transfer within the section. Shift registers with parallel outputs for intra-chip data transfer may be combined with a multiplexer for selecting between parallel data paths and a parallel data output of a local memory for each PE. Similarly, shift registers with serial outputs for inter-chip data tranfer may be combined with a multiplexer for selecting between serial data paths and serial outputs of the shift registers.
Abstract: A switching circuit is described, for selecting between first and second clock signals. When it is desired to switch from the first to the second clock signal, the first clock signal is de-selected in synchronism with the beat of the first clock and then, after a delay, the second clock signal is selected in synchronism with the beat of the second clock. Conversely, when it is desired to switch from the second to the first clock signal, the second clock signal is de-selected in synchronism with the beat of the second clock and then, after a delay, the first clock signal is selected in synchronism with the beat of the first clock. This avoids the possibility of a short pulse or "glitch" at the instant of switch-over.
Abstract: A parallel-to-serial converter is described, comprising a shift register into which a data word can be loaded in parallel and then shifted out serially. As the data is shifted out, a string of zeros is shifted in. When a predetermined number of zeros is detected, a flip-flop is set at the next clock beat. This switches the shift register into its parallel load mode so that, at the next again clock beat the shift register is parallel loaded with the next data word. The detection of the predetermined number of zeros and the setting up of the shift register occur in different clock periods, allowing the clock period to be reduced, thus increasing the speed of operation.