Abstract: Flash memory and process of fabrication in which memory cells are formed with select gates in trenches between stacked, self-aligned floating and control gates, with buried source and drain regions which are gated by the select gates. Erase paths are formed between projecting rounded edges of the floating gates and the select gates, and programming paths extend from the mid-channel regions between the select gates and floating gates through the gate oxide to the edges of the floating gates. Trenched select gates can be provided on one or both sides of the floating and control gates, depending upon array architecture, and the stacked gates and dielectric covering them are used as a self-aligned mask in etching the substrate and other materials to form the trenches.

Abstract: Flash memory and process of fabrication in which memory cells are formed with select gates in trenches between stacked, self-aligned floating and control gates, with buried source and drain regions which are gated by the select gates. Erase paths are formed between projecting rounded edges of the floating gates and the select gates, and programming paths extend from the mid-channel regions between the select gates and floating gates through the gate oxide to the edges of the floating gates. Trenched select gates can be provided on one or both sides of the floating and control gates, depending upon array architecture, and the stacked gates and dielectric covering them are used as a self-aligned mask in etching the substrate and other materials to form the trenches.

Abstract: Self-aligned split-gate NAND flash memory cell array and method of fabrication in which a series of self-aligned split cells are formed between a bit line diffusion and a common source diffusion. Each cell has control and floating gates which are stacked and self-aligned with each other, and a third gate which is split from but self-aligned with the other two. In some disclosed embodiments, the split gates are utilized as erase gates, and in others they are utilized as select gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

Abstract: Flash memory and process of fabrication in which vertically stacked pairs of floating gates and control gates are formed on opposite sides of a source diffusion in a substrate, an erase gate is formed directly above the source diffusion and between the stacked gates, select gates are formed on the sides of the stacked gates opposite the erase gate, programming paths extend from mid-channel regions in the substrate between the select gates and the stacked gates to the edge portions of the floating gates which face the select gates, and erase paths extend from the edge portions of the floating gates which face the erase gates to the source diffusion and to the erase gate. In some embodiments, the source regions are connected electrically to the erase gates, and in others the floating gates project laterally beyond the control gates on one or both sides of the control gates.

Abstract: Memory cell having a floating gate with lateral edges which are aligned directly above edges of the active area in the substrate, a control gate positioned directly above the floating gate, and a select gate spaced laterally from the control gate. The floating gate has a bottom wall and side walls which face corresponding walls of the control gate in capacitive coupling relationship, with the height of the side walls being on the order of 80 to 160 percent of the width of the bottom wall. In some embodiments, the floating gate is wider than the overlying control gate and has projecting portions which overlie the shallow and deep diffusion regions of the stack transistor.

Abstract: Memory cell array and process of fabrication in which a floating gate is formed on a substrate for each of a plurality of memory cells, a control gate is formed above and in vertical alignment with each of the floating gates, source regions are formed in the substrate between and partially overlapped by first edge portions of the floating gates in adjacent ones of the cells, bit lines are formed in the substrate midway between second edge portions of the floating gates in adjacent ones of the cells, and a select gate is formed across the control gates, the floating gates, the bit lines and the source regions.

Abstract: Memory cell array and process of fabrication in which a floating gate is formed on a substrate for each of a plurality of memory cells, a control gate is formed above and in vertical alignment with each of the floating gates, source regions are formed in the substrate between and partially overlapped by first edge portions of the floating gates in adjacent ones of the cells, bit lines are formed in the substrate midway between second edge portions of the floating gates in adjacent ones of the cells, and a select gate is formed across the control gates, the floating gates, the bit lines and the source regions.

Abstract: Memory cell array and process of fabrication in which a floating gate is formed on a substrate for each of a plurality of memory cells, a control gate is formed above and in vertical alignment with each of the floating gates, source regions are formed in the substrate between and partially overlapped by first edge portions of the floating gates in adjacent ones of the cells, bit lines are formed in the substrate midway between second edge portions of the floating gates in adjacent ones of the cells, and a select gate is formed across the control gates, the floating gates, the bit lines and the source regions.

Abstract: Nonvolatile memory cell and process in which a thin floating gate is formed with a rounded lateral edge and a thickness on the order of 100-1000 Å over a gate oxide in an active area on a silicon substrate. A tunnel oxide is formed adjacent to the rounded edge of the floating gate, and a control gate is formed with a lower portion next to the tunnel oxide and an upper portion overlying the floating gate. In some disclosed embodiments, the upper portion of the control gate completely overlies the floating gate, and in others it only partially overlies it.

Abstract: Nonvolatile memory cell and process in which a control gate or a thick dielectric film is used as a mask in the formation of a floating gate and also as a step in the formation and alignment of a select gate. The floating gate is relatively thin and has a side wall with a rounded curvature which, in some embodiments, serves as a tunneling window for electrons migrating to the select gate during erase operations. In other embodiments, the gate oxide beneath the floating gate is relatively thin, and the electrons tunnel through the gate oxide to the source region in the substrate below.

Abstract: Memory cell having a floating gate with lateral edges which are aligned directly above edges of the active area in the substrate, a control gate positioned directly above the floating gate, and a select gate spaced laterally from the control gate. The floating gate has a bottom wall and side walls which face corresponding walls of the control gate in capacitive coupling relationship, with the height of the side walls being on the order of 80 to 160 percent of the width of the bottom wall. In some embodiments, the floating gate is wider than the overlying control gate and has projecting portions which overlie the source and drain regions of the stack transistor.

Abstract: Memory cell having a floating gate with lateral edges which are aligned directly above edges of the active area in the substrate, a control gate positioned directly above the floating gate, and a select gate spaced laterally from the control gate. The floating gate has a bottom wall and side walls which face corresponding walls of the control gate in capacitive coupling relationship, with the height of the side walls being on the order of 80 to 160 percent of the width of the bottom wall. In some embodiments, the floating gate is wider than the overlying control gate and has projecting portions which overlie the source and drain regions of the stack transistor.

Abstract: Nonvolatile memory cell and process in which isolation oxide regions are formed on opposite sides of an active area in a substrate to a height above the substrate on the order of 80 to 160 percent of the width of the active area, a gate oxide is formed over the active area, a first layer of silicon is deposited on the gate oxide and along the sides of the isolation oxide regions to form a floating gate having a bottom wall which is substantially coextensive with the gate oxide and side walls having a height on the order of 80 to 160 percent of the width of the bottom wall, a dielectric film is formed on the floating gate, and a second layer of silicon is deposited on the dielectric film and patterned to form a control gate which is capacitively coupled with the floating gate.

Abstract: The electronically tuned power oscillator (ETPO) of the present invention provides a method and apparatus that drives a narrow-band (high Q) transducer over a relatively broad band of frequencies. A pseudo-random sequence generator dynamically switches a bank of capacitors varying the resonant frequency of the power oscillator. A node on the power oscillator provides the clock for the pseudo-random sequence generator thereby providing a synchronized frequency change on every time varying cycle.