Abstract: A means for reducing the power consumption of the transmitter by storing the recent history of the transmitted data using a string of gates with taps from the string taken at points determined by the propagation delay of each gate and controlling driving transistors as a function of comparison of that history with input data so that, either the signal is driven into the transmission line at full strength, or at a level near the minimum needed to retain the state in the receiver. The advantage of the invention is that the line capacitance decays through the terminating resistors or discharge transistors, such that when the next state change is needed, then line has less stored energy needing to be discharged.

Abstract: The present invention relates to the reduction of artifacts introduced by sending data at a higher rate than the bandwidth of the communication channel, such as the voltage and current offsets introduced in the data at the receiver as a function of the preceding data.

Abstract: The present invention relates in general to the field of generation of precise electrical signals, in particular, to a technique for providing accurate delays of signals using a controllable delay line, and is applicable to the areas of high speed communication and memory testing equipment. According to the present invention, an auxiliary reference channel having a delay line which is identical to the main delay line is incorporated into vernier silicon die to allow automatic adjustment of the delay in the main delay line using a reference periodical signal applied to the auxiliary delay line.

Abstract: A reference voltage generator employs a ring oscillator having a plurality of logic stages and a phase/frequency detector, for generating a first feedback signal on the basis of a phase/frequency difference between the phase/frequency of a reference clock and the phase/frequency of the ring oscillator; and to generate a second feedback signal on the basis of a voltage swing of the oscillator circuit; both feedback signals to be applied to said plurality of logic stages of the ring oscillator; whereby a constant delay is created through each logic stage of the logic device. In another aspects of the invention, a method of generating a reference voltage for a logic device by using the reference voltage generator as above and a logic device with a controlled propagation delay of each of the logic stages are provided.

Abstract: An amplifier circuit for receiving an input signal and providing an output signal, comprises a main chain of logic stages with a plurality of nodes therebetween, and at least one auxiliary chain nested between one node in the main chain and another node, which is not the next node, to form a series of feed back or feed forward nested equalisation loops; whereby the input signal is fed serially down the main chain and is also fed through the said at least one auxiliary chain and summed to provide the output signal. The invention overcomes gain-bandwidth limits of the drive stages and bandwidth reductions that occur when analogue stages operating in a linear mode are concatenated.

Abstract: A method and apparatus for controlling acceleration and velocity of a stepper motor in which a phase offset is selected depending on motor velocity. The optimal phase offset indicates the position of the winding which generates the maximal driving moment. The increase of the driving force and the extension of the range of steady-state movement is achieved for advanced motor coils commutation with constant frequency using velocity feed back and gradual step-wise phase shift where the phase offset is selected depending on rotor velocity. The invention may be effectively applied to servomotors, stepper motors, motors having certain limitations on movement parameters, such as limitations on acceleration and other types of motors.

Abstract: A timing control device and method for minimizing timing uncertainties due to skew and jitter, wherein a device for the compensation of timing errors in multiple channel electronic devices comprises at least one register having a plurality of channels comprising: a clock for providing a clock signal; a reference signal generator for generating reference signals for deskewing the registers. For each register, a corresponding feedback loop is associated for the relative alignment of the register's timing. The feedback loop comprises a device for detecting a deviation from a predetermined level of probability of reading by the register of a desired symbol on a boundary of two reference channel symbols in a sequence, and a set of delay devices which use the detected values of probability to generate a feedback signal.

Abstract: The present invention relates to a coding apparatus for encoding data represented by 8 bit input symbols into 12 bit output codes for serially transmitting the codes along a communication channel, the codes being represented in the channel by signals having a limited minimum and maximum pulse width and sampled by a receiver at each receiver's clock period. The invention reduces artifacts introduced by sending data at a higher payload rate than the bandwidth of the communication channel, such as the voltage and current offsets introduced in the data at the receiver as a function of the preceding data.

Abstract: The present invention relates to a transmitter for high speed communication systems, comprising a plurality, preferably two, drivers each having series terminating resistor, wherein the series terminating resistors are joined at the transmission line. The drivers are controlled in two modes. In the first mode, a control unit supplies drivers with a signal which is a function of input data, to provide the transmitter drives a communication line with an output impedance equal to the parallel effect of all the terminating resistors. In the second mode, the control unit generates a signal to make the drivers with respective series terminating resistors acting as a parallel termination circuit. No actual data is transmitted in this mode. In a preferable embodiment, to achieve this, one driver or a group of drivers drives one logic level signal, while the other drivers drives the inverse to this signal.

Abstract: Bidirectional differential point to point simultaneous high speed signalling is provided between integrated circuits with highly effective echo canceling. Each integrated circuit comprises a transmitter for transmitting a first signal to another integrated circuit and a receiver for receiving a second signal from the other integrated circuit. The transmitter has an output buffer; a receiver has a receiver buffer and is co-located on the same integrated circuit; and a differential buffer is coupled between the input of the transmitter buffer and the output of the receiver buffer. To increase the quality of receiving the second signal, a third signal adjusted in phase and amplitude is coupled at the output of the receive buffer, so that the echoing of the first signal is canceled. Preferably, the rise time of the third signal is also adjusted.

Abstract: An electrical connector for establishing an interconnection between the contact pads of a printed circuit board device under test (DUT) and an electrical device. The connector includes a flexible circuit carrying the interconnect between the DUT and pcb, which is moved into position by the inflation of a bladder that changes its form to press the contacts on the flexible circuit onto the contact positions of the DUT. The bladder is constrained to minimize its expansion. The flexible circuit is not constrained except at the point it is mated with the circuit board of the equipment driving the DUT. The path of the flexible circuit is shaped by fixed formers and terminates at the bladder. This avoids impinging on the DUT area outwith the contact zone. The connector includes variants which have a lock to secure the DUT in place and sensors to determine when the DUT is fully inserted.

Abstract: A high speed communication apparatus with means for reducing timing uncertainty providing a high accuracy of transferring and receiving signals by intelligent skew calibration of the apparatus. The system for reducing timing uncertainty of a communication apparatus comprises a plurality of driving registers for transmitting signals; a plurality of receiving registers for receiving signals; a main clock for generating a main clock signal; a reference clock for generating reference signals for calibrating the registers; and a plurality of phase shift means comprising at least one set of phase shift means associated with each said plurality of registers, for the relative alignment of the register's timing within each plurality.

Abstract: A high precision receiver with a means to reduce or compensate the skew caused by the receiver's hysteresis by using a dynamic reference that is varied depending on a current output signal. To avoid oscillation, the reference signal can be switched over with a certain delay.

Abstract: A method and apparatus for controlling acceleration and velocity of a stepper motor in which a phase offset is selected depending on motor velocity. The optimal phase offset indicates the position of the winding which generates the maximal driving moment. The increase of the driving force and the extension of the range of steady-state movement is achieved for advanced motor coils commutation with constant frequency using velocity feed back and gradual step-wise phase shift where the phase offset is selected depending on rotor velocity. The invention may be effectively applied to servomotors, stepper motors, motors having certain limitations on movement parameters, such as limitations on acceleration and other types of motors.

Abstract: A method for producing a probe unit for contacting an electronic circuit such as a wafer or a die having a predetermined pattern of contact pads deployed in a common plane. The method employes a base plate of made of a material capable of surface uplift when irradiated. On the surface of the base plate locations corresponding to said contact pads are determined. Further, the base plate is irradiated at the determined locations by means of a laser. This results in forming conical surface uplifts. The method further includes plating the conical surface uplifts with an electrically conductive material and providing means for electical connection between said plated conical surface uplifts and an external device.

Abstract: The present invention relates in general to the field of generation of precise electrical signals, in particular, to a technique for providing accurate delays of signals using a controllable delay line, and is applicable to the areas of high speed communication and memory testing equipment. According to the present invention, an auxiliary reference channel having a delay line which is identical to the main delay line is incorporated into vernier silicon die to allow automatic adjustment of the delay in the main delay line using a reference periodical signal applied to the auxiliary delay line.

Abstract: A transmission system and method for transmission of digital data with impedance matching at the terminal ends reduces reflected signals due to impedance mismatch at the terminating ends and due to impedance transition areas in the transmission line. The transmission system includes a transmission line having a driver end connected to a driving circuit and a receiving end connected to a receiving circuit, each said end having an adjustable termination means connected thereto On the driver end of the transmission line said adjustable termination means is incorporated in the driving circuit, while on the receiver end of the transmission line said adjustable termination means is connected in parallel with the receiving circuit. Thus, both the reflections produced on the ends of a transmission line and the reflections resulting from discontinuities within a transmission line will be terminated.

Abstract: The present invention relates generally to the transmission of digital data. More particularly, the invention relates to a high-speed data transmission between integral circuits (ICs) or chips. A data transmission means for high-speed transmission of digital data is proposed, the data transmission means comprising: at least one driver for driving a transmission line; and a timing deskewing means connected thereto, wherein the timing deskewing means comprises a storage means for recording and storing information on skew caused by inter-symbol interference and cross-talk influence in the transmission line, for at least one data pattern transmitted through the transmission line; and an adjustment means for generating and applying a correction to the timing position of a signal transition between two logical levels, the correction being generated on the basis of the information stored in the storage means, so as to compensate for the above skew.

Abstract: Automatic test equipment for memory device testing provides continuous high-speed testing by intelligent pausing a timer when a buffer memory is full or nearly full, the timer being paused is capable of properly maintaining refresh and clock functions for semiconductor devices.

Abstract: A system for transformation of memory device addresses between different memory device topologies, each topology having its address space, providing the use of minimum memory space and time required for storage and computing defect data and also the flexibility of approach which allows mapping of memory device divided into an arbitrary number of tiles, each tile having different mapping scheme from a wide spectrum of mapping classes.