Abstract: For a programmable Logic Array (PLA) having a nominal operating voltage, a method for ensuring reliable operation of the PLA during a configuration memory read operation comprises steps of (a) providing an intentionally weak pass gate for memory cells in the configuration memory, too weak to flip latches of the memory cells with nodes of the cells powered at the nominal operating voltage; and (b) powering the nodes of the cells with a voltage-controlled source, allowing voltage for the nodes to be reduced during write so latches may be flipped by the weak passgate, and allowing voltage to return to the nominal higher value during read, such that the weak pass gates cannot flip latches. A memory cell with such a weak passgate and operating characteristics is taught, a configuration memory using such cells, and a Programmable Logic Array with such a configuration memory.

Abstract: A novel architecture for a multi-scale programmable logic array (MSA) to be used in the design of complex digital systems allows digital logic to be programmed using both small-scale blocks (also called gate level blocks) as well as medium scale blocks (also called Register Transfer Level or RTL blocks). The MSA concept is based on a bit sliceable Arithmetic Logic Unit (ALU). Each bit-slice may be programmed to perform a basic Boolean logic operation or may be programmed to contribute to higher-level functions that are further programmed by an ALU controller circuit. The ALU controller level in this new approach also allows the primitive logic operations computed at the bit-slice level to be combined to perform complex random logic operations. The data shifting capability of this new programmable logic architecture reduces the complexity of the programmable routing needed to implement shift operations including multiplier arrays.

Abstract: A memory system with an operating voltage of Vcc has a memory cell with first and second inverters connected input to output to make a latch defining a Q node and a QB node, and powered by a single voltage controlled Vmm line. There is a passgate transistor connected source to drain from a BIT line to the first inverter, the passgate having a strength low enough that, with Vmm substantially equal to Vcc and the gate of the passgate energized at Vcc by a WORD signal, no signal on the BIT line can flip the latch. Circuitry is provided for reducing the voltage of Vmm during a write cycle, so a signal on the BIT line may flip the latch. In preferred embodiments the memory system is applied to Programmable Logic Arrays.