Abstract: Improved speaker independent speech recognition system and method are disclosed in which an utterance by an unspecified person into an electrical signal is input through a device such as a telephone, the electrical signal from the input telephone converting the electrical signal into a time series of characteristic multidimensional vectors, the time series of characteristic multidimensional vectors are received, each of the vectors being converted into a plurality of candidates so that the plurality of phonemes constitutes a plurality of strings of phonemes in time series as a plurality of candidates, the plurality of candidates of phonemes are compared simultaneously (one at a time) with a reference pattern of a reference string of phonemes for each word previously stored in a dictionary to determine which string of phonemes derived from the phoneme recognition means has a highest similarity to one of the reference strings of the phonemes for the respective words stored in the dictionary using a predetermine

Abstract: The sequencer (14) is part of a computational system (10) which includes a computational circuit component, or processor node array (16); the sequencer, or controller component (14); and a boundary interface (34) between the computational circuit component (16) and the controller component (14). The controller component (14) provides three main functions in the system: (one) it sequences computations in a computational component (16), which includes an array of processor nodes (74, 76, 78, 80, 82, 84); (two) it provides I/O processing (20) from several disparate sources between the processor node array (16) and a host processor (12); and (three) it synchronizes data flow from a substantially asynchronous portion of the system (12) with a substantially synchronous data flow in the processor node array portion of the system (16).

Abstract: A virtual-zero architecture is intended for use in a single instruction stream, multiple data stream (SIMD) processor which includes an input bus, an input unit, manipulation units, an output unit and an output bus. The virtual-zero architecture includes a memory unit (40) for storing data, an arithmetic unit (42) for mathematically operating on the data, a memory address generation unit (32) and an adder for computing a next memory address. The memory address generation unit (32) includes an address register (34) in the memory unit for identifying the address of a particular data block, a counter (38) for counting the number of memory addresses in a particular data block, and a rotation register (36) for providing a data-void address in the memory unit if and only if all of the entries in the data block are zero. The memory (40) and the address (32) units provide zero-value data blocks to the arithmetic unit (44) to simulate the data block having the data-void address during processing.

Abstract: A bit disposal apparatus includes a register (16) which is divided at a truncation point (14) into a left register segment (18) and a right register segment (28), wherein bits to be disposed of are contained in the right register segment. A decision mechanism initially examines the bits in the right register segment (28) and transmits a "1" signal (60) if and only if any of the bits in the right register segment is a "1". If any of the bits in the right register segment is a "1", a 1 is "jammed" into the least significant bit location (26a) of a result register (26a).

Abstract: A concurrent computation/communication architecture is intended for use in a single instruction stream, multiple data stream (SIMD) processor node which includes an input bus (20), an input unit (54), manipulation units (58, 60, 62, 64, 66) and an output bus (22). Processor nodes (12, 14, 16, 18) include an output unit (68) which receives data from the input unit (54) and the various manipulation units. Processor nodes (12, 14, 16, 18) store and transmit data from the output unit (68) at a selected time over the output bus (22). A processor node control unit (56) is provided for controlling the exchange of data between the processor nodes (12, 14, 16, 18), their associated output buffers (38, 40, 42, 44) and the output bus (22).