Abstract: A structure of an integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform suicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.
Type:
Grant
Filed:
October 17, 2005
Date of Patent:
December 11, 2007
Assignee:
Adavnced Micro Devices, Inc.
Inventors:
Robert J. Chiu, Jeffrey P. Patton, Paul R. Besser, Minh Van Ngo