Abstract: An encryption and decryption method applied upon transmitting a plaintext in a communication network containing plural subscriber ends is provided.

Abstract: A transmission component for processing priority packets supported by using a single chip's buffer structure. Packets of network data are divided into high priority packets and low priority packets. High priority packets in the component are sent first, followed by low priority packets in order to satisfy priority requirement. Moreover, packets are transmitted continuously without stopping to maintain packet transmission at high performance. Furthermore, the transmission component of the present invention is compatible with different kinds of chip structure, and therefore no hardware must be changed when applied to different kinds of chip structure.

Abstract: Current applications used in security system for encryption/decryption/authentication require intense CPU computation for an SAD search. Therefore, a part of the SAD is planted into an ASIC in order to lessen the load of the CPU. The invention provides a high-performance lookup method that is “LIFM” adapted to the ASIC. Initially, the ASIC makes a perfect match by comparing the SAD_index field of all items allocated in the ASIC with an incoming packet to fetch the required SAD_key. If there is no match, the software and hardware are started by issuing an interrupt from the ASIC until the CPU finds a perfectly matched item. Then, the software level updates the perfectly matched item in the ASIC.

Abstract: This invention discloses a dynamic memory allocation method for an Ethernet switching architecture, which can resolve problems with the limitations of transmission bandwidths and transmission port counts in a conventional network packet switching. The method comprises steps of providing a plurality of input ports and output ports, providing a shared memory for storing packet segments of a plurality of packets, providing a first link RAM (Random Access Memory) for controlling a making and reading of a single linked list for the packet segments of each the plurality of packets, and providing a second link RAM serving as a FIFO (first in first out) device for co-managing an obtaining of the link address spaces at the corresponding input ports before the single linked list been made, and a releasing of the link address spaces at the corresponding output ports after the single linked list been read.

Abstract: A wireless transmission apparatus comprises a wired network port for exchanging data with a computer, a wireless network port including a radio frequency circuit module, a processing unit for converting the format of the data transmitted between the wired network port and the wireless network port, and a power port electrically connected to a universal series bus (USB) port of the computer by which the wireless transmission apparatus is powered. The wireless transmission apparatus can further comprise a power controller electrically connected to the power port, wherein the power controller comprises a voltage transformer adapted to convert a voltage of the power port into a voltage suitable for the operation of the wireless transmission apparatus and a power-saving controller adapted to suspend the power supply to the radio frequency circuit module according to a power control signal generated by the processing unit.

Abstract: An output buffer circuit with low-voltage devices to driver high-voltage signals for PCI-X applications is proposed. Because power supply voltage of PCI-X is at 3.3V, the high-voltage gate-oxide stress is a serious problem to design PCI-X I/O circuit in a 0.13 ?m 1V/2.5V CMOS process with only low-voltage gate oxide. This proposed output buffer circuit can be operated at 133 MHz in 3.3V PCI-X environment without causing high-voltage gate-oxide reliability problem. In this design, the circuit is implemented in a 0.13 ?m 1V/2.5V CMOS process and the output signal swing can be 3.3V. Besides, a level converter that converts 0V˜1V voltage swing to 1V˜3.3V voltage swing is also presented.

Abstract: A power-rail ESD clamp circuit for mixed-voltage I/O buffer is proposed. The power-rail ESD clamp circuit comprises an ESD detection circuit and an ESD protection device. Under normal operating condition, the ESD detection circuit will not trigger the ESD protection device, and therefore the component used in the circuit will not have the gate-oxide reliability issue and also will not generate undesirable leakage current. Under ESD-zapping conditions, the ESD detection circuit will provide some trigger voltage or current to bias the ESD protection device. The ESD protection device can be triggered on quickly to discharge the ESD energy efficiently.

Abstract: A signal detection method with high detection probability and low false alarm rate is provided for spread spectrum communication systems. The method includes steps of a) receiving discrete-time input signal, b) converting the input signal into a correlator output signal with finite number of values, c) selecting a maximum value and a minimum value from the magnitude of values, respectively, d) dividing the maximum value by the minimum value for obtaining an enhanced peak value of the correlator output signal, and e) comparing the enhanced peak value of the correlator output signal with a predetermined threshold, wherein the input signal is detected as a spread spectrum signal if the enhanced peak value of the correlator output signal is greater than or equal to the predetermined threshold, whereas the input signal is not detected as a spread spectrum signal if the enhanced peak value of the correlator output signal is less than the predetermined threshold.

Abstract: The comparator includes a differential stage having a first input and a second input, an output stage in which the output is zero when the two inputs have therebetween a specific voltage difference, and a biasing stage providing a first biasing voltage and a second biasing voltage for respectively creating a second input voltage and a first input voltage respectively in the second and first inputs such that the two input voltages have therebetween the specific voltage difference. A method for forming the same includes steps of a) providing the differential stage, b) providing the output stage and c) providing the biasing stage which has a characteristic dependent on a manufacturing parameter such that the specific voltage difference is independent of the manufacturing parameter.

Abstract: A flow control signal system in a switch and a processing method for a flow control signal system to control the data packets transmitted in network is disclosed. The flow control signal system in a switch includes an empty buffer counter, N port-packet-counters and N alarm units therein. And a processing method is also provided, which includes steps of sending and storing the data packet into a switch, respectively computing the both values of the empty buffer counter and the port-packet-counters, alarming an alarming state for informing a port in the switch will be overfilled with the data packets, triggering one of (N−1) alarm units for stopping other data packets from source ends connected with the another ports in network to be transported to the switch and running the steps disclosed in the present invention to process the data packets until all data packets in the switch have been processed.

Abstract: The invention relates to a multi-output monolithic device, and particularly to a multi-output monolithic integrated circuit device without generating a simultaneous switch output (SSO) in communication or in a network, in which the plurality of output port will not switch from "0" to "1" or from "1" to "0" simultaneously to prevent insufficient power supply caused by a simultaneous switch, resulting in noise generation and errorous operations. A multi-bit shift register in used in the invention to make each output port have a different and to reduce the probability of the same output value on each output port, thereby reducing the influence of SSO. Then, a slightly different delay is made of each output port during output, so as to eliminate SSO.

Abstract: The present invention provides a reliable method for oscillating an oscillator having an oscillator output without fail. The method includes steps of detecting whether the oscillator is regularly oscillating, and releasing the oscillator to oscillate when the oscillator is regularly oscillating, and holding the oscillator from oscillating until an enough control voltage is built-up therefor when the oscillator is not regularly oscillating. The present invention also provides a start up circuit for an oscillator having an oscillator output having a first state in a first instance and a second state in a second instance.